“Scaling the walls of sub-14-nm manufacturing” was the topic of a keynote panel discussion kicking off SEMICON West Tuesday morning. Jo de Boeck, senior vice president for corporate technology at imec served as moderator. Panelists included Calvin Cheung, vice president, ASE; Gary Patten, CTO, GLOBALFOUNDRIES; Subhasish Mitra, associate professor of electrical engineering and computer science, Stanford; and Michael Campbell, senior vice president of engineering, Qualcomm.
Moore’s Law is 50 this year, observed de Boeck, who asked the panelists what threat it faces going forward. Patten commented that seasoned old people talk about end of scaling. However, scaling is not going to end, he said. Moore’s Law has faced many “insurmountable” barriers over the years, and all have been surmounted. For example, when gate oxide reduced to three atomic layers, the industry adopted high-k metal gates. Now, companies are adopting finFETs and planar fully depleted devices. “What worries me is not physics challenges,” he said, “but the ability to deliver to our customers a value proposition for going to a new node.
Campbell said he sees the big threat is end-to-end yield—not just semiconductor yield, but package and system yield as well. Cheung agreed, adding that interconnect is of particular concern. He said that with scaling, the silicon die is getting smaller, but the I/O is increasing, adding to the challenges faced by OSATs such as ASE.
Mitra offered two points. First, avoid linear thinking in favor of nanosystems thinking—focusing not just on the next transistor but on system-level performance issues related to extreme 3D integration. Second, he said, bugs that should have been found pre-silicon are often found post-silicon, requiring weeks or months of manual debug. What’s needed, he said, is a way to automate the process and complete it overnight.
Campbell made the point that the ability to find a bug in a billion-transistor linear array is difficult enough, but today most silicon requires complex code developed on top plus RF capability. Raw transistor count provides only a first-order indication of the challenges involved.
Cheung said that from an OSAT perspective it’s increasingly challenging to support silicon from different foundries—given chip/package interaction. Further, it is no longer to take six months for yield ramp, given a 9-month mobile product lifetime.
The panelists all agreed that cooperation is necessary. Campbell called for a “team sort” in which everyone speaks the same language. However, Cheung noted that as technology gets more complex, he senses a reluctance from ASE’s partners to disclose information. “Moving forward, we have to do that more effectively,” he said.
Patten concluded, “Orders-of-magnitude improvement is possible though innovation.” Brain circuits, he suggested, are not high speed, lack an interconnecting bus structure, and are low-power and reconfigurable—perhaps suggesting a roadmap for future devices. “I see a lot of potential and hope for the future,” he added.
