In conjunction with SEMICON West last week, imec made news that it disclosed at its imec Technology Forum (ITF) July 13 and throughout the week. The news related to RRAM, thermocompression solution for narrow-pitch die-to-wafer bonding, low-temperature passivation, a perovskite photovoltaic module, and pore-sealing low-k dielectrics in advanced interconnects.
Imec and Panasonic announced that they have fabricated a 40-nm TaOx-based RRAM (resistive RAM) technology with precise filament positioning and high thermal stability. This breakthrough result paves the way to realizing 28-nm embedded applications.
One of today’s most promising concepts for scaled memory is RRAM, which is based on the electronic (current-or voltage-induced) switching of a resistor element material between two metals. Imec and Panasonic developed a method that overcomes filament instability in RRAM, one of the critical parameters that impacts the memory state during read operation in resistive memory.
The method was realized using a combination of process technologies such as low-damage etching, cell-side oxidation, and an innovative encapsulated cell structure with an Ir/Ta2O5/TaOx/TaN stacked film structure featuring a filament at the cell center. With these methods, a 2-Mbit 40-nm TaOx-based RRAM cell with precise filament positioning and high thermal stability was achieved. The memory array showed excellent reliability of 100k cycles and 10 years’ retention at 85°C. Additionally, the filament control and thermal stability technologies offer the potential to realize 28nm cell sizes.
Gosia Jurczak, director of imec’s research program on RRAM devices, stated, “With these breakthrough results, we have proven the potential of this promising memory concept as embedded nonvolatile memory in 28-nm technology node where conventional NOR Flash shows scaling limitations. This result is a confirmation of our leadership position in research and development on resistive memory.”
Thermocompression
Also, imec and Besi, a global equipment supplier for the semiconductor and electronics industries, announced that they have jointly developed an automated thermocompression solution for narrow-pitch die-to-wafer bonding, a method by which singulated dies are stacked onto bottom dies which are still part of a fully intact 300-mm wafer. The solution features high accuracy and high throughput, paving the way to a manufacturable 2.5D, 3D, and 2.5D/3D hybrid technology.
3D IC technology, stacking multiple dies into a single device, aims to increase the functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics, such as smartphones and tablets, which require smaller ICs that consume less power.
One of the challenges to making 3D IC manufacturing an industrial reality is the development of a high-throughput automated process flow for narrow-pitch, high-accuracy die-to-die and die-to-wafer bonding. Thermocompression bonding (TCB) is a widespread process used by the industry for highly accurate die-to-package bonding. The method released the stress in the laminate layer and avoided stress to build up between the two stacked layers. Yet, more traditional approaches to thermocompression bonding come with long cycle times (>1 minute per die), meaning significant improvements in throughput are required to enable this stacking approach on a 300-mm wafer.
Imec and Besi have developed an automated TCB process on 300 mm wafers for Besi’s new 8800 TC bonder tool. Imec and Besi demonstrated die-to-wafer bonding at high accuracy, sufficient for 50 µm pitch solder micro bump arrays and a throughput of >1000 UPH with a dual bond head configuration.
“Collaborating with imec, leveraging their expertise on fine pitch bonding materials and processes, has enabled us to develop our 8800 TC bonder tool according to the needs of the semiconductor industry,” said Hugo Pristauz at Besi. “This collaboration has helped us to offer our customers a viable and effective solution for 2.5D/3D IC manufacturing, especially for the new C2W applications.”
Dry silicon removel
imec and SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor and related industries, announced at SEMICON West that they are jointly developing a highly accurate, short cycle-time dry silicon removal and low-temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in wafer-to-wafer bonding.
Wafer backside processing is critical for 3D-IC wafer stacking. Today, through-silicon vias (TSV) formed using via-middle processing, are typically exposed from the backside of 300-mm device wafers by a combination of mechanical grinding and wet or dry etch processes. Dielectric layers are then deposited by plasma enhanced chemical vapor deposition (PECVD) to passivate and mechanically support the exposed TSVs prior to bump/RDL (redistribution) formation, followed by chip-to-wafer or wafer-to-wafer bonding.
To develop an industrially viable 3D-IC technology, the via reveal process requires a shorter cycle time etching process. Additionally, due to accumulating non-uniformities coming from the TSV frontside etching, bonding, and grinding processes, variations of a few microns may occur in residual silicon thickness above the via tips. Therefore, a highly selective process to thin TSV liners and smooth post-etch surfaces is essential to achieve the necessary precision and control within wafer uniformity.
Imec and SPTS are developing a dry etching solution that features in-situ end-point detection. This enables controlled and very precise processing. The process achieves the required TSV height while avoiding lengthy and multiple rework steps thus minimizing the overall cost per wafer. Our first results demonstrate that 1.57-µm nail height can be controlled within 300-nm range (see image below).
To follow the via reveal etch step, imec and SPTS will also work on PECVD dielectric passivation stacks, with SiO and SiN layers deposited at temperatures below 200°C. Films will be engineered to optimize device electrical performance and stress-managed to minimize warpage of the thin die after debonding.
The collaboration will use SPTS’s Versalis fxP system, a single-wafer cluster platform carrying both etch and dielectric deposition modules to be installed into imec’s 300-mm packaging line in Q3 2015.
“Equipment suppliers are key in developing an integrated solution for the challenges of scaling technology into advanced nodes,” said An Steegen, senior vice president for process technology at imec. “The collaboration with SPTS confirms imec’s direction to accelerate innovation for all our partners by closely interacting with suppliers at an early stage of development.”
“Imec plays a critical role in the long term development of the entire semiconductor value chain, from front to back-end,” said Kevin Crofton, president of SPTS and corporate vice president at parent company Orbotech. “Their pre-competitive work supports the roadmaps of their core customers. Their remit dictates that they work with vendors and processes that are enabling for imec and their partners, and to be selected is a huge endorsement of our capabilities. We look forward to the results and milestones that we will achieve together.”
Imec’s research into 3D-IC includes key partners such as GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK Hynix, Sony, and TSMC.
Perovskite photovoltaic module
Imec also announced a record 11.3% aperture and 11.9% active area efficiency for its thin-film perovskite photovoltaic (PV) module. The efficiency was measured over an aperture area of 16 cm2. This achievement is the best conversion efficiency for perovskite modules in literature.
Organometal halide perovskites are considered an excellent material for thin-film solar cells as they have shown high conversion efficiencies at cell level. While the power conversion efficiency of this new class of thin film solar cells has increased rapidly in the last few years, further improvements are still needed to make thin-film photovoltaics an attractive technology for industrial production. Larger area processing and narrow interconnections are prerequisites for processing efficient thin-film modules.
Imec’s perovskite module achieves a geometrical fill factor of more than 95% and an aperture conversion efficiency of 11.3%. The active area efficiency was demonstrated with 11.9%. These record devices have been fabricated by the conventional lab scale spin coating process. Imec also used a linear coating technique (blade coating) for all the solution based layers, to prove industrially viable fabrication methods. By using this method, the modules achieved a 9% aperture area efficiency. These achievements are important breakthroughs in bringing thin-film solar technology to industrial scalability for applications such as building integrated photovoltaics (BIPV).
“Imec is steadily improving the conversion efficiencies of its perovskite solar cells and at the same time adjusting the fabrication processes to enable industrial adoption of this promising technology,” said Tom Aernouts, R&D manager for thin-film photovoltaics at imec. “Leveraging our expertise in organic photovoltaics enables us to make rapid progress in enhancing the conversion efficiencies, ultimately aiming at conversion efficiencies of more than 20% for this type of thin-film solar cells.”
Imec develops a platform for glass-based perovskite modules and collaborates with Solliance, a cross-border Dutch-German-Flemish thin-film PV research initiative. Thanks to its high power conversion efficiency and stand-alone integration in building elements, both glass-based and thin-film perovskite PV technology are widely considered as important technologies for the BIPV market. Moreover, imec is exploring stacking a perovskite cell on top of a silicon solar cell to increase the conversion efficiency of silicon solar cells. The perovskite cell will capture the light which is not absorbed by silicon, as such enabling conversion efficiencies of more than 30%.
Pore-sealing low-k dielectrics
And finally, imec said it has demonstrated concept and feasibility for pore-sealing low-k dielectrics in advanced interconnects. The method, based on the self-assembly of an organic monolayer, paves the way to scaling interconnects beyond N5.
The need for ultra-porous low-k materials as interconnect dielectrics to meet the requirements dictated by the ITRS (International Technology Roadmap for Semiconductors) poses several challenges for successful IC integration. One of the most critical issues is the indiffusion of moisture, ALD/CVD metal barrier precursors and Cu atoms into the porous low-k materials during processing (low-k pore diameter larger than 3 nm, up to 40% porosity). This leads to a dramatic increase of the material dielectric constant and leakage current, and to the reduction of the voltage for dielectric breakdown.
Imec has developed a method to seal the pores of the low-k material with a monomolecular organic film. The method not only prevents diffusion of moisture and metal precursors into the low-k material, it also might provide an effective barrier to confine copper within the copper wires and prevent copper diffusion into the low-k material.
Self-assembled monolayers (SAMs) derived from silane precursors are deposited from vapor phase on 300-mm wafers into low-k during chemical vapor or atomic layer deposition and subsequent Cu metallization. The dielectric constant (k) of the resulting sealing layer is 3.5 and a thickness lower than 1.5 nm was achieved. This is key to limit the RC delay increase enabling beyond 5-nm technology nodes. As a result, a ca. 30% capacitance reduction was observed after SAM pore-sealing was applied. Moreover, a clear positive impact on the low-k breakdown voltage is observed upon sealing.
