HIPPEROS adds acceleration, IPC, scheduling to multicore RTOS

Feb. 27, 2017

Louvain-la-Neuve, Belgium. HIPPEROS S.A., a developer of real-time and embedded high-performance-computing software designed to improve efficiency and reliability, has added a series of features—including hardware acceleration, fast multicore inter-process communications (IPC), and mixed-criticality scheduling—to its HIPPEROS multicore real-time operating system (RTOS) for high-performance embedded systems. The new features are released in HIPPEROS version 17.02, which is available now and will also be showcased at Embedded World 2017 March 14-16 in Nuremberg.

HIPPEROS RTOS is a family of ITAR-free, highly configurable, modular and parallel real-time operating systems (RTOS) designed specifically for multicore platforms for the next-generation of reliable, low-power, hard real-time, high-performance embedded systems. HIPPEROS’s modularity and configurability enables different kernels to be tailored to satisfy specific application requirements, adapting to different use cases. Its low-footprint hard real-time kernel enables the smooth co-ordination of a mix of software and hardware tasks without missing a single deadline.

The new features in HIPPEROS v17.02, which include hardware acceleration, fast multicore IPC, and mixed criticality scheduling, make it suited to computer vision applications for use cases such as drone navigation, medical imaging, and advanced driver assistance systems (ADAS). A high video frame rate is key for many computer-vision applications, and RTOS hardware acceleration means that tasks can be handled by an on-board FPGA rather than the CPU as a way of achieving 90 video frames per second. Fast multicore IPC enables tasks running on different processors to speedily exchange data by message passing, which is essential for parallel, multithreaded processes that would otherwise have a major impact on system performance. With mixed criticality scheduling, both high and low criticality tasks can be run on the same board with the RTOS taking care of the critical priorities, thereby reducing the number of systems needed and overall costs, weight, power consumption, etc.

“Most currently available RTOSs in the market were not originally designed for multicores. Consequently, they do not scale well and their design is not able to cope efficiently with the challenges of multicore architectures or growing application demands which tends either to compromise safety or result in an inefficient use of computing resources,” said Ben Rodriguez, CEO/CTO of HIPPEROS S.A. “With the announcement of HIPPEROS v17.02 we are introducing very innovative features, including hardware acceleration, fast multicore IPC, and mixed criticality scheduling, that will ensure it continues to fill the multicore performance gap while remaining totally reliable for use in the next generation of high-performance applications such as computer vision.”

At Embedded World 2017, the company will demonstrate the use of the HIPPEROS RTOS in two principal applications: a low-power image-processing application on a Sundance board with a Xilinx Zynq Ultrascale 7000 chip, using the RTOS hardware acceleration capabilities coupled with the FPGA to achieve video frame rates up to 20 times faster than using the CPU only, and parallel AES encryption on a SabreLite board.

HIPPEROS was founded in 2014 and is headquartered in Louvain-la-Neuve, Belgium. The company is a spin-out of the research university Université Libre de Bruxelles (ULB), and specializes in the development of efficient and reliable real-time and embedded high-performance computing software solutions. Principal products include the HIPPEROS family of configurable, modular, and parallel real-time operating systems (RTOS) designed for the next generation of high-performance embedded multicore computing platforms. Targeted at safety-critical applications in markets including aerospace, automotive, avionics, defense, robotics, industrial control, medical devices, and vision systems, the HIPPEROS RTOS kernel uses an architecture specifically designed for parallelism, state-of-the-art scheduling and resource sharing algorithms.

HIPPEROS is a founding member of the TULIPP (Towards Ubiquitous Low-power Image Processing Platforms) consortium, which is funded under the European Union’s Horizon 2020 program. HIPPEROS also benefits from R&D funding support from the European Space Agency’s Business Incubation Centre for space-related technologies and Belgium’s Wallonia regional government Plan Marshall program regarding DO-178 avionics certification.

http://www.hipperos.com

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