1Q silicon wafer shipments increase quarter-over-quarter to record level

May 14, 2018

Milpitas, CA. Reaching their highest recorded quarterly level ever, worldwide silicon wafer area shipments jumped to 3,084 million square inches during the first quarter 2018, a 3.6% increase over fourth quarter 2017 area shipments of 2,977 million square inches and a 7.9% rise over first quarter 2017 shipments, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

“Global silicon wafer shipment volumes started the year at historic levels,” said Neil Weaver, chairman, SEMI SMG, and director, product development and applications engineering at Shin-Etsu Handotai America. “As a result, silicon shipments, like device shipments, are positioned to be strong this year.”

Silicon* Area Shipment Trends

Millions of Square Inches
1Q 2017
2Q 2017
3Q 2017
4Q 2017
1Q 2018
Total
2,858
2,978
2,997
2,977
3,084

Source: SEMI, May 2018

All data cited in this release includes polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as nonpolished silicon wafers shipped by the wafer manufacturers to end users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon, or silicon wafers (for example, as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

*Semiconductor applications only.

www.semi.org

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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