San Francisco, CA. SEMICON West-related events got underway Monday with the imec Technology Forum USA (ITF USA). Ajit Manocha president and CEO of SEMI, welcomed the “brainpower” in attendance and noted that imec and SEMI have much in common in promoting innovation in the semiconductor industry. He commended imec not only for its precompetitive research but for truly promoting innovation. Despite predictions about the demise of Moore’s Law, Manocha said, the semiconductor industry continues to innovate in applications ranging from healthcare to smart cities.
Luc Van den hove, imec president and CEO, then commented on new perspectives in creating radical innovation. “Aspire to do the impossible,” he advised. “Thinking beyond what we know is essential. We invite you to look at things from an unusual perspective.” Van den hove cited Apollo astronaut Al Worden, who would not have undertaken his voyage to the moon had he believed it to be impossible.
He said the ITF USA could not delve in to all of imec’s activities but would highlight key areas, including healthcare. He noted that we are living longer, but that often means living with illness. Our focus shouldn’t be only on lifespan but also on “healthspan.” To that end, he said, “We need new cell-interfacing tools—today’s technology falls short.”
imec’s latest initiative is a multi-electrode-array (MEA) chip, which offers single-cell resolution. “We can parallelize enormous amounts of testing to measure what couldn’t be measured before at speeds not imagined before,” he said. The technology can detect the early onset of disease and guide selection of the right medication.
Van den hove then turned his attention to big data, noting that we are generating a zettabyte of data per year. “Is an ever growing cloud the answer?” he asked. A view of the problem from a different perspective suggests that machine-learning technology compatible with battery-powered devices may offer a solution.
Van den hove also commented on imec’s work with batteries and smart cars, leading potentially to zero crashes, zero emissions, and zero congestion. He also touched on neuromorphic computing and quantum computing. He closed by thanking imec’s 3,500 researchers and many industry partners for making the impossible possible.
Several presenters from imec and industry followed Van den hove, discussing topics ranging from memory to silicon photonics. And in conjunction with ITF USA, imec made three announcements focused on hybrid FinFET-silicon photonics technology, 3-nm technology, and sequential-3D integration.
First, imec said it has demonstrated ultralow power, high-bandwidth optical transceivers through hybrid integration of silicon photonics and FinFET CMOS technologies. With a dynamic power consumption of only 230 fJ/bit and a footprint of just 0.025 mm2, the 40-Gb/s non-return-to-zero optical transceivers mark an important milestone in realizing ultradense, multi-Tb/s optical I/O solutions for next-generation high-performance computing applications.
The exponentially growing demand for I/O bandwidth in datacenter switches and high-performance computing nodes is driving the need for tight co-integration of optical interconnects with advanced CMOS logic, covering a wide range of interconnect distances (1 m to 500 m+), imec said. In the presented work, a differential FinFET driver was co-designed with a silicon photonics ring modulator and achieved 40-Gb/s NRZ optical modulation at 154-fJ/bit dynamic power consumption. The receiver included a FinFET transimpedance amplifier (TIA) optimized for operation with a Ge waveguide photodiode, enabling 40-Gb/s NRZ photodetection with an estimated sensitivity of -10 dBm at 75-fJ/bit power consumption. High-quality data transmission and reception was also demonstrated in a loop-back experiment at 1,330-nm wavelength over standard single-mode fiber (SMF) with 2-dB link margin. Finally, a 4 x 40-Gb/s, 0.1-mm2 wavelength-division multiplexing (WDM) transmitter with integrated thermal control was demonstrated, enabling bandwidth scaling beyond 100Gb/s per fiber.
Second, imec reported on the potential of using ruthenium (Ru) as a disruptive interconnect material for 3-nm and beyond technology nodes. High-aspect ratio Ru lines were shown to outperform conventional Cu metallization in two different implementation scenarios: in buried power-rail applications and as interconnects for advanced memory and logic applications by using subtractive metal etch.
Due to an increasing resistance-capacitance delay and rising reliability concerns, the use of dual-damascene Cu as a process flow for back-end-of-line interconnect fabrication has become questionable beyond the 5-nm technology node. To maintain the scaling paths, imec has therefore been pioneering and pipelining the potential replacement of this conventional Cu technology. Interconnects based on Ru are a promising candidate, because of their resistance to oxidation, high melting point, low bulk resistivity, and the ability to build barrier-less interconnect modules. ITF presenter Zsolt Tokei, distinguished member of the technical staff at imec, said, “For more than five years, imec has been systematically investigated this disruptive alternative, from the fundamentals to module-level implementation. The results have recently come to the point of strong industrial interest.”
And finally, imec in collaboration with Soitec reported that they successfully demonstrated a sequential 3D front-end integration process by stacking two device layers on one another on a 300-mm wafer. This vertical integration of sequentially processed device layers, also named sequential-3D integration (S3D), is perceived as a promising alternative to continue the benefits offered by semiconductor scaling, overcoming the constraints of geometrical scaling while maintaining the benefits of functional scaling through the vertical 3D integration.
The most critical challenge of sequential-3D integration is the management of the fabrication thermal budget. To avoid or limit thermally induced device degradation issues of the bottom device layer, the top device layer must be processed at low temperatures below 525°C. The top thermal budget needs to be reduced to avoid degradation of the bottom devices, the bottom interconnects, and the bonding interface, according to imec. These limitations are overcome with the implementation of junction-less transistors on the top layer, which decreases the fabrication complexity and provides sufficient device reliability.
