Over the past several decades, wireless system channel counts and bandwidths have steadily increased. The driving factors for these modern telecommunication, radar, and instrumentation systems are their data rate and overall system performance requirements.
However, these requirements have also increased power envelopes and system complexities, making power density and component level features more important. The semiconductor industry is addressing some of these limitations by integrating more channels on the same silicon footprint and integrating more complex features into digital front ends.
This technical article presents experimental results utilizing a 16-channel transmit and 16-channel receive subarray in which all transmit and receive channels are calibrated using hardened DSP blocks within the digitizer integrated circuit (IC).