Implementing An Efficient RTL Clock Gating Analysis Flow
April 4, 2017
Sponsored by Mentor Graphics
Lowering the power consumption of consumer products and networking centers is an important design consideration. The same goes for many of the processor cores that go into these devices.
This paper provides an overview of how a leading semiconductor company used PowerPro to improve clock-gating efficiency, and shares the results and advantages of doing power analysis at the RTL stage rather than waiting until post-gate synthesis.
