The synchronous buck converter is a widely used topology in low-voltage, high-current applications. One common application is a point-of-load (POL) converter that transforms a system bus voltage of 48 V, say, to 1 V or below to power high-performance microprocessors, FPGAs, or ASICs.
Figure 1 shows the schematic of a synchronous buck converter. The circuit replaces the diode in the basic buck circuit with a low-side (LS) FET chosen for low RDS(ON). The FET costs more than a diode, but enhances converter efficiency. Learn more about synchronous versus nonsynchronous buck converters here.
Synchronous buck designs can achieve efficiencies over 90%. At these levels, improving performance requires both a good understanding of the sources of power loss and a fanatical dedication to reducing them further.
An ideal switching converter, or course, has zero power losses. When an ideal power switch is open, it has infinite resistance; thus, the current through it is zero. When the switch is closed, it has zero resistance, so the voltage across it is zero. In both states, there’s zero power loss; the switch also switches between the two states in zero time.