Sponsored by Mentor, a Siemens Business
A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. Read how they were able to solve these challenges and improve their verification quality and efficiency by reading this white paper.