Mentorpaper 106029 Port

How to Convert your Vivado Designs to Catapult High-Level Synthesis

March 3, 2020
A solution for when you need to either switch FPGA technologies, or to an ASIC.

Sponsored by Mentor, a Siemens Business

Often, your idea starts off as an FPGA prototype. But what if you need to switch FPGA technologies or to an ASIC? Instead of being locked into a Xiliinx® Vivado® HLS flow, learn how to port that design into the Catapult HLS flow. In that flow, you will experience the flexibility to pick any technology without changing your source code. And, you gain access to a powerful verification toolset to quickly and completely verify your design at the C/C++ level. Learn how to make this port in this whitepaper.