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Automated and Context-Aware Latch-Up Checking

May 19, 2020
This white paper reviews how the increase in the number of power domains and voltages used in today's IC design has increased the importance of identifying and eliminating areas of susceptibility to latch-up.

Latch-up susceptibility continues to be a growing concern for IC designers and verification engineers alike.  Not only for Bulk designs, but also for FD-SOI which leverages hybrid bulk technologies for their IO devices. The good news is that context-aware latch-up verification can be automated to identify and validate the inadvertent structures and spacing requirements that make these checks so difficult to implement in traditional EDA tools. 

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