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Automated and Context-Aware Latch-Up Checking

May 19, 2020
This white paper reviews how the increase in the number of power domains and voltages used in today's IC design has increased the importance of identifying and eliminating areas of susceptibility to latch-up.

Latch-up susceptibility continues to be a growing concern for IC designers and verification engineers alike.  Not only for Bulk designs, but also for FD-SOI which leverages hybrid bulk technologies for their IO devices. The good news is that context-aware latch-up verification can be automated to identify and validate the inadvertent structures and spacing requirements that make these checks so difficult to implement in traditional EDA tools. 


A Deep Dive into Audio Jack Switches and Configurations

The audio jack is an industry-standard connector that has many potential uses in addition to providing basic audio connectivity.

What is the Most Effective Way to Commutate a BLDC Motor?

Brushless direct current electric motors, or BLDC motors for short, are electronically commutated motors powered by a dc electric source via an external motor controller. Unlike...

MEMS versus ECM: Comparing Microphone Technologies

Increasing numbers of devices utilize microphones to capture sound. Two of the most commonly used microphone technologies are MEMS and ECM.

A Designer's Guide to Lithium (Li-ion) Battery Charging

This designer's guide helps you discover how you can safely and rapidly charge lithium (LI-ion) batteries to 20%-70% capacity in about 20-30 minutes.