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Accelerate early design exploration & verification for faster time to market

Jan. 27, 2021
Want to find and fix integration issues early in the design cycle of your SoC? Learn how targeted checking can help.

Early chip-level physical verification faces many challenges. The Calibre™ Recon tool enables design teams to perform analysis and physical verification of full-chip design layouts during very early stages of the design cycle, while the different components are still immature. With Calibre Recon, designers can quickly and easily find and resolve integration issues using the foundry/IDM Calibre sign-off design kit, while reducing total DRC runtime, accelerating design closure, and ensuring high-quality designs.

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