Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization, but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R tools during digital implementation provides immediate feedback on targeted window-based DRC fixes. P&R engineers can spend less time running batch DRC, so they can focus on producing high-quality, optimized designs.
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