• Complex Ate Flow F8 D3 Ff51 5cc7617bbc722

    Whitepaper: Accelerating Test Pattern Bring-Up for Rapid First Silicon Debug

    Feb. 18, 2019
    This standard silicon bring-up flow is becoming too slow and expensive, especially for very large designs with complex DFT structures. This whitepaper from Mentor Graphics explains how to speed up the silicon bring-up process.
    Ee 0219 Mentor Wp 200px
    Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially for very large designs with complex DFT structures.

    Download the whitepaper here

    Continue Reading

    Sponsored

    Stricter guidelines imposed by version 3 of the IEC standard for harmonic current emissions push designers to embrace power-factor-correction methodologies.
    The flyback topology is a versatile, widely used, switched-mode power-supply design with some interesting characteristics that brings performance and BOM advantages to many applications...
    Designing power supplies that work from wall outlets has multiple challenges. This FAQ should answer many of your questions.
    High output current, also referred to as Iout, might be an important spec for your low-dropout (LDO) linear regulator.