Aprisa Infographic 1 62ffdf7db8b20

Reducing IC design effort with easy-to-use reliable digital IC design flow

Aug. 19, 2022
IROC Technologies faced developing an integrated circuit (IC) - from scratch - with limited internal IC design resources. To meet the aggressive tapeout schedule, IROC needed to feel confident in the new design flow and software.

IROC Technologies faced developing an integrated circuit (IC) - from scratch - with limited internal IC design resources. To meet the aggressive tapeout schedule, IROC needed to feel confident in the new design flow and software.

There's little flexibility for errors in mission-critical applications such as in aerospace. The IC would act as a test vehicle for a slew of testing, so getting a quality chip without many iterations would speed the overall project.

Download now to see how IROC Technologies leveraged a new place-and-route tool to tapeout an SoC in three months.

This content is sponsored by:

Sponsored

Learn how Single Pair Ethernet (SPE) contributes to sustainability in industrial communication. This on-demand webinar explores how SPE reduces wiring, installation costs, and...
Autonomous mobile robots enhance flexible manufacturing. Key design areas include battery management, motor control, localization, and 3D perception. Modular solutions support...
Discover the key differences between an LCR meter and a VNA, and learn when to use each tool for optimal results. This episode demystifies these complex instruments with straightforward...
5G is here. Increased speed, capacity, and bandwidth. TE Connectivity has powerful solutions to 5G communications connectivity design obstacles.