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What Is JESD204 and Why We Should Pay Attention to It?

April 3, 2020
In this first article of a 12-part series, learn more about the JESD204 protocol and how it will change how we design.

Series: The JESD204 Story

A new converter interface is steadily picking up steam and looks to become the preferred protocol for future converters. This new interface—JESD204—was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.

The steadily increasing resolution and speed of converters has pushed demand for a more efficient interface. The JESD204 interface brings this efficiency and offers several advantages over its complementary metal-oxide semiconductor (CMOS) and low-voltage differential-signaling (LVDS) predecessors in terms of speed, size, and cost.

Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, a reduction in pin count leads to smaller package sizes and a lower number of trace routes that make board designs much easier and offer lower overall system cost. The standard is also easily scalable so that it can be adapted to meet future needs. This has already been exhibited by the two revisions that the standard has undergone.

Since its introduction in 2006, the JESD204 standard has seen two revisions and is now at Revision B. As the standard has been adopted by an increasing number of converter vendors and users, as well as FPGA manufacturers, its been refined, and new features have been added that increased efficiency and ease of implementation. The standard applies to both analog-to-digital converters (ADCs) as well as digital-to-analog converters (DACs), and is primarily intended as a common interface to FPGAs (but may also be used with ASICs).

JESD204—What Is It?

TheoriginalversionofJESD204wasreleased in April 2006.Thestandard describesamultigigabitserialdatalinkbetweenconverter(s) andareceiver, typically a device such as an FPGA or ASIC. In this original version of JESD204, the serial data link was defined for a single serial lane between aconverterormultipleconvertersandareceiver (Fig. 1).

The lane shown is the physical interface between M number of converters and the receiver, which consists of a differential pair of interconnects utilizing current-mode-logic (CML) drivers and receivers. The link shown is the serialized data link that’s established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.

The lane data rate is defined between 312.5 Mb/s and 3.125 Gb/s, with both source and load impedance defined as 100 Ω ±20%. The differential voltage level is defined as being nominally 800 mV p-p with a common-mode voltage-level range from 0.72 to 1.23 V. The link utilizes 8b/10b encoding that incorporates an embedded clock, removing the necessity for routing an additional clock line and the associated complexity of aligning an additional clock signal with the transmitted data at high data rates.

It became obvious, as the JESD204 standard began gaining popularity, that the standard needed to be revised to incorporate support for multiple aligned serial lanes with multiple converters. This would accommodate the increasing speeds and resolutions of converters.

This realization led to the first revision of the JESD204 standard, which became known as JESD204A. This revision of the standard added the ability to support multiple aligned serial lanes with multiple converters. The lane data rates, supporting from 312.5 Mb/s up to 3.125 Gb/s, remained unchanged as did the frame clock and the electrical interface specifications.

Increasing the capabilities of the standard to support multiple aligned serial lanes made it possible for converters with high sample rates and high resolutions to meet the maximum supported data rate of 3.125 Gb/s. Figure 2 shows a graphical representation of the additional capabilities added in the JESD204A revision to support multiple lanes.

Although both the original JESD204 standard and revised JESD204A standard were higher performance than legacy interfaces, they still lacked a key element. This missing element was deterministic latency in the serialized data on the link. When dealing with a converter, it’s important to know the timing relationship between the sampled signal and its digital representation. It’s then possible to properly recreate the sampled signal in the analog domain once the signal has been received (this situation is, of course, for an ADC; a similar situation is true for a DAC).

This timing relationship is affected by the latency of the converter, which is defined for an ADC as the number of clock cycles between the instant of the sampling edge of the input signal until the time that its digital representation is present at the converter’s outputs. Similarly, in a DAC, the latency is defined as the number of clock cycles between the time the digital signal is clocked into the DAC until the analog output begins changing.

In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the converter and its serialized digital inputs/outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard—JESD204B.

The Arrival of JESD204B

In July of 2011, the second and current revision of the standard, JESD204B, was released. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the data rates supported were pushed up to 12.5 Gb/s, broken down into different speed grades of devices. This revision of the standard calls for the transition from using the frame clock to using the device clock as the main clock source. Figure 3 gives a representation of the additional capabilities added by the JESD204B revision.

In the previous two versions of the JESD204 standard no provisions were defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link resynchronization events, the latency should be repeatable and deterministic.

One way to accomplish this is by initiating the initial lane-alignment sequence in the converter(s) simultaneously across all lanes at a well-defined moment in time by using an input signal called SYNC~. Another implementation is to use the SYSREF signal, which is a newly defined signal for JESD204B. The SYSREF signal acts as the master timing reference and aligns all of the internal dividers from device clocks as well as the local multiframe clocks in each transmitter and receiver. This helps to ensure deterministic latency through the system.

The JESD204B specification calls out three device subclasses: Subclass 0—no support for deterministic latency; Subclass 1— deterministic latency using SYSREF; and Subclass 2—deterministic latency using SYNC~. Subclass 0 can simply be compared to a JESD204A link. Subclass 1 is primarily intended for converters operating at or above 500 MSPS, while Subclass 2 is primarily for converters operating below 500 MSPS.

In addition to the deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gb/s and divides devices into three different speed grades. The source and load impedance is the same for all three speed grades being defined as 100 Ω ±20%.

The first speed grade aligns with the lane data rates from the JESD204 and JESD204A versions of the standard and defines the electrical interface for lane data rates up to 3.125 Gb/s. The second speed grade in JESD204B defines the electrical interface for lane data rates up to 6.375 Gb/s. This speed grade lowers the minimum differential voltage level to 400 mV p-p, down from 500 mV p-p for the first speed grade. The third speed grade in JESD204B defines the electrical interface for lane data rates up to 12.5 Gb/s. This speed grade lowers the minimum differential voltage level required for the electrical interface to 360 mV p-p. As the lane data rates increase for the speed grades, the minimum required differential voltage level is reduced to make physical implementation easier by reducing required slew rates in the drivers.

To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were the same. This didn’t offer a lot of flexibility and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths.

In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver is given its respective device clock from a clock generator circuit that’s responsible for generating all device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.

JESD204—Why We Should Pay Attention to It

In much the same way as LVDS began overtaking CMOS as the technology of choice for the converter digital interface several years ago, JESD204 is poised to tread a similar path in the next few years. While CMOS technology is still hanging around today, it has mostly been overtaken by LVDS. The speed and resolution of converters as well as the desire for lower power eventually renders CMOS and LVDS inadequate for converters. As the data rate increases on the CMOS outputs, the transient currents also increase and result in higher power consumption. While the current, and thus, power consumption, remains relatively flat for LVDS, the interface has an upper speed bound that it can support.

This is due to the driver architecture, as well as the numerous data lines that must all be synchronized to a data clock. Figure 4 illustrates the different power-consumption requirements of CMOS, LVDS, and CML outputs for a dual 14-bit ADC.

At approximately 150 to 200 MSPS and 14 bits of resolution, CML output drivers start to become more efficient in terms of power consumption. Due to the serialization of the data, CML offers the advantage of requiring fewer output pairs per a given resolution than LVDS and CMOS drivers. The CML drivers specified for the JESD204B interface have an additional advantage since the specification calls for reduced peak-to-peak voltage levels as the sample rate increases and pushes up the output line rate.

The number of pins required for the same given converter resolution and sample rate is also considerably less. The table compares the pin counts for the three different interfaces using a 200-MSPS converter with various channel counts and bit resolutions. The data assumes a synchronization clock for each channel’s data in the case of the CMOS and LVDS outputs and a maximum data rate of 4.0 Gb/s for JESD204B data transfer using the CML outputs. The reasons for the progression to JESD204B using CML drivers become obvious when looking at the table and observing the dramatic reduction in pin count that’s possible.

Analog Devices, a market leader in data converters, has seen the trend thats pushing the converter digital interface toward the JESD204 interface defined by JEDEC. The company has been involved with the standard from the beginning, when the first JESD204 specification was released. To date, Analog Devices has released several converters to production with JESD204- and JESD204A-compatible outputs and is currently developing products with outputs that are compatible with JESD204B.

For example, the AD9639 is a quad-channel, 12-bit, 170/210-MSPS ADC that has a JESD204 interface. The AD9644 and AD9641 are 14-bit, 80/155-MSPS dual and single ADCs that have the JESD204A interface. From the DAC side, the recently released AD9128 is a dual 16-bit, 1.25-GSPS DAC with a JESD204A interface. For more information on Analog Devices’ JESD204 efforts, visit


The increasing speed and resolution of converters has escalated the demand for a more efficient digital interface. The industry began realizing this with the JESD204 serialized data interface. The interface specification has continued to evolve to offer a better and faster way to transmit data between converters and FPGAs (or ASICs). The interface has undergone two revisions to improve upon its implementation and meet the increasing demands brought on by higher speeds and higher-resolution converters.

Looking to the future of converter digital interfaces, it’s clear that JESD204 is poised to become the industry choice for the digital interface to converters. Each revision has answered the demands for improvements on its implementation and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performance pushes higher, the JESD204 standard should be able to adapt and evolve to continue to meet the new design requirements necessary.

Jonathan Harris is a product applications engineer in the High Speed Converter Group at Analog Devices.

Series: The JESD204 Story


JEDEC Standard JESD204 (April 2006). JEDEC Solid State Technology Association.

JEDEC Standard JESD204A (April 2008). JEDEC Solid State Technology Association.

JEDEC Standard JESD204B (July 2011). JEDEC Solid State Technology Association.

About the Author

Jonathan Harris | Applications Engineer, Analog Devices Inc.

Jonathan Harris is a product applications engineer in the High Speed Converter Group at Analog Devices (Greensboro, N.C.). He has over seven years of experience as an applications engineer, supporting products in the RF industry. Jonathan received his MSEE from Auburn University and his BSEE from UNC-Charlotte. In his spare time, he enjoys mobile audio, nitro RC, college football, and spending time with his two children.

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