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IEEE's Two-fer Deal: Two Virtual Symposia on VLSI Technology & Circuits for One Fee

June 8, 2020
Instead of being held in Waikiki, Hawaii, this year's IEEE joint symposium on VLSI Technology & Circuits will take place in cyberspace.

Although the pandemic has put many aspects of our lives on hold, we'll still be able to attend the IEEE's double-feature Symposia on VLSI Technology & Circuits in Cyberspace from June 15-18, 2020. To celebrate its 40th anniversary, the event is organized around the theme “The Next 40 Years of VLSI for Ubiquitous Intelligence,” and will be held on a fully overlapping schedule online. A single registration fee includes both events.

The two Symposia have been held together since 1987, providing an opportunity for the world’s top device technologists and circuit and system designers to exchange leading-edge research on microelectronics technology, with alternating venues between Hawaii and Japan. Presented for the first (and hopefully last) time as a completely virtual conference, the Symposia provide a unique forum for conversations between device technologists and circuit/systems designers in the emerging fields of machine learning, IoT, AI, wearable/implantable biomedical applications, big data, cloud/edge computing, robotics, and autonomous vehicles.  The virtual conference program will include technical presentations, plenary sessions, panel discussions, joint focus sessions, and Short Courses presented in an online format.

The virtual Symposium on VLSI Technology & Circuits will hold Short Courses on June 15 and a forum session dedicated to edge intelligence topics on June 17. A single registration enables participants to attend both Symposia.

The Symposia program provides a unique perspective on the microelectronics industry by integrating the technology ecosystem of converging industry trends. The advanced circuit design and application platforms will realize the future promise of “ubiquitous intelligence.”

The weeklong virtual conference will feature technical presentations, plenary sessions, panel discussions, joint focus sessions, and the aforementioned Short Courses presented in an online format. Additional information and registration  can be accessed here:

The entire program can be viewed at, but some of the highlights are posted below.

Program Highlights

Plenary Sessions (June 15 and 17)

The first plenary session on June 15 will include “5G Evolution and 6G” by Takehiro Nakamura, Sr. VP & GM, 5G Laboratories, NTT DOCOMO, and “Silicon is Greener: Why Innovation in Circuits is Needed for Sustainability,” by Jen Lloyd, VP, Precision Technology & Platforms Group, Analog Devices.

The second plenary session on June 17 will include “The Future of Compute: How the Data Transformation is Reshaping VLSI,” by Michael C. Mayberry, CTO,  Intel Corp., and “Empowering Next-Generation Applications through FLASH Innovation” by Shigeo (Jeff) Ohshima, technology executive at KIOXIA (formerly Toshiba Memory).

Joint Focus Sessions

The event's interdisciplinary program elements include a series of joint focus sessions to present contributed papers from the Technology and Circuits programs. Topics will include: “Silicon Photonics,” “5G / mm-wave,” “System-Technology Co-Optimization (STCO) / Design-Technology Co-Optimization (DTCO),” and “MRAM Future – Opportunities Beyond Spin-Torque Transfer (STT).”

Panel Sessions (June 16 & 18)

The Technology panel discussion on June 16, moderated by Gary Bronner, Rambus, addresses the question: “Memory & Logic Technology Divergence: Will AI/ML Bring Them Back Together?

The topic of the evening Circuits panel session, held on June 18, is “Human vs. Machine: The Future Role of AI/Machine Learning in Circuit Design.”

Short Courses (June 15)


  • “Future of Scaling for Logic & Memory” will cover a range of topics, including nanosheet transistors, on-die interconnect challenges, a review of previous memory scaling challenges, ferroelectric hafnium-oxide applications in memory, and the use of EUV lithography.
  • “More than Moore” will address emerging technologies for TSV-free monolithic 3D ICs, in-situ BELO transistors and oxides, and layer transfer technologies for heterogeneous integration.


  • “Trends & Advancement in Circuit Design” will address a variety of topics, including topologies of switched capacitor converters, noise-shaping SAR ADC techniques, next-generation resistor-based sensors, time reference and frequency generation, ultra-miniaturized wireless transceiver IC design, high-speed serial links for high-density I/O applications, and design considerations for emerging memories and in-memory computing.
  • “Heterogeneous Integration – To Boldly Go Where No Moore Has Gone Before,” is a Joint Technology/Circuits Short Course that  will cover a range of topics, including chiplet design benefits and limitations, heterogeneous system partitioning, back-end (OSAT) 2.5D/3D solutions, heterogeneous integration for AI, 3D packaging for MEMS and sensors, I/O circuits, tools and flows, and design strategies for memories.

 “Friday” Forum (June 17)

The Symposia program will include a virtual forum session (formerly known as the Friday Forum)—a series of presentations focusing on “Technologies & Circuits for Edge Intelligence.” It’s led by experts in the field who will help guide participants in discussions on the contributions of technology and circuits needed to drive the future of advanced edge computing.

Workshops (June 16 and 17)

Held before the main Symposia technical sessions begin, these workshops provide additional learning opportunities for participants. Workshop topics include:

  • “Know Where You Are Going: Metrology in the New Age of Semiconductor Manufacturing”
  • “Analog Computing Technologies & Circuits for Efficient Machine Learning Hardware”
  • “Quantum Computing: Maximizing the Impact of the Semiconductor Industry”

Additional  information and registration can be accessed here:

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