Vladimir Timofeev | Dreamstime.com
Data Center Speed Promo

Clock and Data Recovery Plus AI Will Fuel the Data Center

Oct. 18, 2021
In this Q&A, Semtech’s Timothy Vang discusses how CDR solutions and AI development will optimize the data-center and wireless industries.

What you’ll learn:

  • How clock and data recovery (CDR) solutions will further advance HPC technology.
  • What differentiates CDR technology from DSP technology?
  • How AI and ML will be implemented into data centers in the future.

It’s all about timing. This includes everything from the operation of microprocessors to the communication links between devices and systems. Technologies like pulse amplitude modulation 4-level (PAM4) are the basis for very-high-speed serial communications. One of the aspects for proper operation is clock and data recovery (CDR).

I talked with Timothy Vang, Vice President of the Signal Integrity Products Group at Semtech, about how CDR solutions and artificial-intelligtence (AI) development can help optimize the operation of data center and the wireless industries.

Can you provide background on Semtech and its Tri-Edge technology?

Semtech’s Tri-Edge PAM4 CDR technology is the first analog PAM4 retiming product platform available on the market for optical communication links. The technology addresses the data-center and high-performance-computing (HPC) markets, as well as the 5G wireless fronthaul, midhaul, and backhaul markets, with the vast majority of links being within 100 m to 40 km.

How does Semtech’s Tri-Edge solution address compliance and regulatory issues in the data-center industry?

Tri-Edge enables optical module solutions meeting IEEE compliance that are also fully compliant with Open Eye MSA specifications for short-reach (SR) and long-reach (LR) links. Semtech is a founding member of the Open Eye MSA, formed to develop a full ecosystem of optics, ICs, modules, and test equipment to support them.

The Open Eye MSA developed industry-standard optical interconnects allowing for a wide variety of architectures, technologies, and standardized specifications to improve interoperability and lessen the complexities and costs of production testing. The Tri-Edge products are deployed in optical links for both Open Eye and IEEE standards.

How will clock and data recovery solutions optimize the data center and wireless industries? Will this further advance HPC technology?

CDRs are low-power, low-latency, and low-cost analog solutions that have been key to advancing high-volume optical interconnects. Most hyperscale data centers are transitioning from 100G NRZ modules to higher data rates using PAM4, and the Tri-Edge analog CDR platform is designed to optimize that transition. Current DSP implementations for PAM4 consume higher power than Tri-Edge solutions.

Integration is a major factor in Tri-Edge’s low-power capabilities. Having an integrated IC with both CDR and PMD (VCSEL, DML or EML drivers, or TIA) in a monolithic solution enables optimization of the signal integrity at the lowest overall power. Integration eliminates the power associated with chip-to-chip interfaces in the optical module, and integration means fewer chips, fewer interfaces, lower costs, and a smaller footprint. These same advantages apply to PAM4 optical links in the wireless market. 

For HPC applications, the low power and low latency of analog CDRs are important. In HPC architectures, lowering interconnect power allows for more compute power to be deployed, and the lower latency of analog increases the CPU utilization as data is available faster.

What differentiates CDR technology from DSP technology, and what typically draws customers to one or the other?

DSP technology for 50G and 100G optical links uses advanced CMOS processes to enable the analog-to-digital sampling required to digitize the incoming high-speed signal, allowing digital processing to improve the signal integrity. This is followed by a digital-to-analog conversion to retransmit the outgoing signal. Such a method of improving signal integrity often has additional computing overhead (and related power) to enable the link performance. 

Analog CDR technology preserves the analog nature of the incoming signal and uses optimized equalization and signal conditioning to improve the signal integrity. Analog can be optimized for various link requirements to deliver a low-power, low-latency, and low-cost solution. DSP may be preferred where the additional digital compute capability can be used for added performance, but at the cost of added power. The Analog CDR solution is preferred where power, latency, and cost are premiums.

How do you see AI development being implemented into data centers in the future?

Low power is vital for AI-centric data centers as processing consumes vast amounts of energy, leaving less for data interconnects, including optical interconnects. Machine-learning (ML) requires high throughput, with low power and latency for processing. Based on customer conversations, AI servers will have significantly more interconnects, making the cost of the optical interconnects critical as well. 

While the architecture of the data center depends critically on the servers and switches, it also depends on the cost, reach, and throughput of these interconnects. Tri-Edge will enable data centers to move to higher data rates (from 100G to 400G and 800G). The future AI, supercomputing, and 5G wireless infrastructure markets will also benefit from the low power, cost and latency factors that come with CDR technology.

What current Tri-Edge applications would you like to highlight?

Tri-Edge CDRs consist of a family of solutions that address data center and 5G wireless optical interconnect needs from 100 m up to 40 km, enabling 50-Gb/s PAM4 Grey, fixed-WDM (wavelength division multiplexing), tunable WDM, and silicon-photonics optical modules. The solutions offer ultra-low-latency, low-power, and low-cost 25-Gb/s bandwidth optics to operate at 50-Gb/s PAM4.

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