January 30, 2013. Mentor Graphics today at DesignCon announced the newest release of its HyperLynx product for high-speed design and analysis. Key features in the new HyperLynx product release include advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance—up to 5X faster. Engineers and designers who use the HyperLynx products during the system design process can quickly analyze potential high-speed design issues that can impact signal integrity, power integrity, and electromagnetic-interference (EMI) performance. These new capabilities will improve product quality and performance by correcting problems earlier in the design process with minimized risk and greater productivity.
“In applications above 10 Gbps, insertion loss will often exceed -12 dB at the Nyquist [rate] and eyes will be completely closed. Successful designs require getting everything in the design right and building confidence in the design early in the design cycle with accurate simulations,” stated Eric Bogatin, signal integrity evangelist at Bogatin Enterprises, a wholly owned subsidiary of Teledyne-LeCroy. “The accuracy of the latest release of Mentor Graphics HyperLynx was recently validated with a 12.5-Gbps backplane design from Molex that included causal material models, copper surface texture contributions, via models, mode conversion, and reflections from integrated S-parameter models of connectors.”
Channel and Trace Modeling
The new HyperLynx product decreases the amount of channel modeling that requires 3D analysis with advanced area fill-aware 2.5D planar trace extraction. When this feature is enabled, the system will model variations in signal trace impedance or delays due to non-ideal planes and references (complex area fills with voids and cuts). The resulting impedance variation effects are included during time domain simulation and s-parameter model extraction.
Where necessary, the HyperLynx product also provides full 3D extraction and modeling. The designer can quickly select board areas for 3D full wave analysis, including exporting the full channel to the schematic editor for auto-port creation, assignment, and simulation, tightly integrating the HyperLynx 3D EM full wave solver.
The newest release of the HyperLynx product provides fast analysis results, with an average of 5X simulation performance improvement over the previous release. Internal tests of earlier versions and the new HyperLynx product release show a significant increase in the performance of the circuit simulator, especially for large-scale batch-mode analysis with complex stimulus (for example, DDRx simulation). In addition to substantially increased performance, the upgraded simulator takes extra care to avoid accuracy problems for circuits involving short transmission lines, which are common when modeling PCB-trace meanders.
The new HyperLynx release supports prelayout DDRx signal-integrity and comprehensive cycle-based timing simulation during parametric sweeps. The HyperLynx DDRx wizard supports DDR3L and DDR3U supply levels by incorporating the required derating tables, timing models, and voltage levels, plus test-load compensation of signal launch delays using the DDRx wizard. It offers batch support of S-parameter models from the post-route environment and interconnect modeling with accurate wideband dielectric models and surface roughness. It also offers advanced meshing for DC drop analysis, accelerated simulation flow of IBIS AMI models in statistical mode with LTI equalization algorithms, and improvements to the waveform viewer and processor, including an interactive simulation GUI that automatically plots centered eye diagrams.
The new HyperLynx release will ship in March 2013 and will be interfaced with all major PCB layout tools including the Mentor Expedition Enterprise, Board Station, and PADS; Cadence Allegro; and Zuken CR.