24-Bit ADC Boasts Tight Specs Plus Superior Design-In Simplicity

Analog-to-digital converters (ADCs) are the critical interface between the real world of sensors and signals and the digitized, processor- and software-driven system. Given their countless operating scenarios, it’s not surprising that thousands of distinct such converters are available from dozens of sources, with each one offering a blend of performance, packaging, power, and price attributes to be best-matched to the application priorities.

The right ADC can make a system design flow smoothly, while one that’s a lesser fit may require either performance compromises or significant effort to overcome its inadequacies—if that’s even possible. Vendors continue to add new ADCs to their roster to fit applications, take advantage of IC design advances, and leverage process improvement.

Among the latest wave of releases (yes, new ADCs keep coming at a fast rate) is Analog Devices’ AD4630-24, a two-channel, simultaneous-sampling, 2-Msample/s successive-approximation-register (SAR) ADC (Fig. 1). With a guaranteed maximum ±0.9-ppm integral nonlinearity (INL) and no missing codes at 24 bits, the AD4630-24 achieves extreme precision from −40 to +125°C.

However, these specifications and similar ones alone don’t fully characterize this converter. ADI boasts that this device incorporates its patented Easy Drive technology and versatile Flexi-SPI serial peripheral interface (SPI) to minimize system design-in challenges and broaden the selection of directly compatible companion products. (Of course, no vendor acknowledges that their product is hard to use—it’s all a matter of relative degree.)

The company maintains that the EasyDrive approach assures performance while eliminating many traditional system-level design challenges such as strict layout guidelines. In addition, the Flexi-SPI digital interface helps smooth ADC integration with the host processor by providing easy-to-meet timing requirements.

The wide differential input and common-mode ranges allow inputs to use the full ±V_REF range without saturating, simplifying signal-conditioning requirements and system calibration. Low-power operation is another benefit at 15 mW per channel at 2 Msamples/s and dropping down to 1.5 mW per channel at 10 ksamples/s.

Additional device attributes include:

• Typical accuracy performance to 0.1 part per million (ppm) and signal-to-noise ratio (SNR) value of 105.7 dB.
• Small solution size: 7- × 7-mm, 64-ball package with internal power-supply and reference capacitors to reduce system footprint and component count.
• Wide common-mode input range ensures compatibility with both single-ended and differential-input signal chains.
• A wide data-clocking window, multiple SDO lanes, and optional dual-data-rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 Msamples/s.
• Echo clock mode and ADC master clock mode relax the timing requirements and simplify the use of digital isolators.

The 49-page datasheet provides the expected minimum/maximum performance and absolute maximum specifications. In addition, numerous tables and graphs characterize behavior from many perspectives including, but not limited to, SNR and signal-to-noise and distortion (SINAD) versus input frequency (Fig. 2) and total harmonic distortion (THD) versus input frequency and amplitude (Fig. 3).

Further design support is provided via the EVAL-AD4630-24FMCZ Evaluation Board ($199), which is designed for use with a Digilent ZedBoard used to control data capture and buffering (Fig. 4).

The evaluation board connects to the ZedBoard board via a field-programmable gate-array (FPGA) mezzanine card (FMC) low-pin-count (LPC) connector and includes a voltage reference, clock source, and ADC drivers. The ZedBoard connects to a PC through a USB interface.

There’s an overview and links to other resources at the ADC product page and a one-minute video here. The dual-channel AD4630-24 and single-channel AD4030-24 are available now ($30.95 in 1,000-piece lots); the four additional derivative SAR ADCs are expected later this year.