Cadence Design Systems has started infusing artificial intelligence (AI) into its flagship suite of chip design software to help chip designers build better chips faster than they could alone.
Now, it is also powering up its system design software with AI to help companies build electronic devices and systems around those chips. Cadence’s latest AI platform, called Optimality Intelligent System Explorer, plugs into its multiphysics system analysis software to automatically identify areas for improvement at the system level.
The San Jose, California-based company said the AI technology would help improve productivity. It will allow engineers, on average, to design and qualify electronic devices 10X faster than traditional manual methods.
Cadence is one of the leading vendors of electronic-design-automation (EDA) software used in chip design. It is also a major player in multiphysics software used to dial in different aspects of a system, ranging from the heat dissipation of a chip’s packaging to the integrity of the power and signal delivery on a circuit board.
“For years, optimization at the system level has been extremely inefficient,” with engineers moving from design to prototyping to mass production, with testing and adjustments at every step of the process, said Ben Gu, head of the company’s multiphysics system analysis business.
With Optimality Explorer, “it’s now possible to perform system-level optimization, from the IC to the package, the PCB and the system, in a fraction of the time and with Cadence’s signature gold-standard accuracy.”
AI-Designed Chips
Last year saw the arrival of the Cerebrus Intelligent Chip Explorer, which uses a unique reinforcement-learning engine. It employs AI technology to automate parts of the chip design process and propose improvements to chip designs, minimizing engineering effort and time to tape out.
One problem Cadence is trying to solve with Cerebrus is chip floorplanning. Chip placement requires carefully configuring up to thousands of different components in a compact three-dimensional space.
The reinforcement-learning engine at the heart of the Cerebrus technology learns to optimize the placement of building blocks on the chip in a way that makes it less power-hungry and reduces die area.
Reinforcement-learning uses positive and negative feedback to learn a complicated task instead of relying on specific instructions on how to accomplish it. Cadence said that it rewards the AI when it moves closer to the performance and power-efficiency goals for the chip, signaling that it should continue. Conversely, when AI alters the chip design in a way that has the opposite effect, the system gives it a virtual penalty. Over time, Cerebrus converges on a strategy for optimally placing components on a floorplan.
MediaTek was one of the early customers of the Cerebrus optimization technology, using it to reduce the die area of a key component inside one of its processors by 5% and power consumption by more than 6%.
AI-Analyzed Systems
Now, it is bringing similar AI technology to its multiphysics computational software, including its Clarity Solver for 3D electromagnetic (EM) analysis and SigrityX to assess signal (SI) and power integrity (PI).
With Optimality Explorer, Clarity and Sigrity X solvers help improve productivity by allowing engineers to explore vast numbers of possible system designs and converge on one with optimal electrical performance.
The tool is also designed whereby customers can extend AI-driven optimization across Cadence’s multiphysics technologies to create a full computational software suite, spanning simulation, optimization, and signoff.
Ease of use is another major advantage, said the company. Customers can activate the Optimality Explorer technology inside Clarity 3D and SigrityX environments when faced with a challenging design problem.
One early customer for the AI system design software is Microsoft, which pairs Optimality Explorer with Cadence’s Clarity 3D Solver to test circuit boards ahead of mass production.
“The Optimality Explorer’s AI-driven optimization allowed us to uncover novel designs and methodologies that we would not have achieved otherwise,” said Kyle Chen, principal Hardware Engineer at Microsoft.
General availability is expected in the fourth quarter of 2022.