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There are many ways, and just as many opinions on the best method, to configure grounds for ADCs and other mixed-signal products. An earlier article written by the author ("Attack The Noise Gremlins That Plague High-Speed ADCs," Electronic Design, Dec. 17, 1999, p. 107) discussed the limitations of popular ADC grounding techniques and suggested a split ground plane. Though the method works for obtaining good noise performance for high-speed ADCs, a split ground plane isn't good for RFI/EMI performance.
Despite that grounding problem, there is a way to enhance noise performance while minimizing layout-related radiation. Three concepts dictate how to handle grounding for a combination of good dynamic performance and minimal RFI/EMI: the skin effect, the proximity effect, and a layout that considers these effects. The skin effect indicates that at high frequencies, the conductor's effective cross-sectional area is reduced below the actual full cross-sectional area. The proximity effect is when a flow of return current in the reference plane is restricted to a narrow area below or above the trace carrying the corresponding outgoing current.
This article discusses the difficulties surrounding skin and proximity effects and offers methods to deal with them. Among the topics are use of power traces instead of power planes, careful component placement, and the grounding of open areas. In particular, attention to component placement and power-supply routing makes it possible to achieve low noise performance while providing acceptable RFI/EMI levels.
|The Skin Effect||When ac flows primarily near the outside surface of the conductor, or on its skin, that is the skin effect. It becomes more prominent as frequency increases. Therefore, the effective cross-sectional area of the conductor is smaller than the actual dimension.|
|The Proximity Effect||The magnetic field surrounding outgoing and return currents causes those currents to want to flow in close proximity to each other, ultimately restricting the return current to a narrow area below or above the trace.|
|Performance Needs||Three fundamental principles help determine what's necessary for best overall performance: all currents follow the path of least impedance; transmission-line impedance is proportional to the distance between conductors; and the amount of signal-path radiation increases with the loop area defined by the outgoing and return current paths.|
|Grounding Open Areas||It's common practice to cover all unused areas on the top and bottom of the pc board with grounded copper. Copper areas should be grounded at more than one point to avoid an antenna effect that would result in radiated energy at the frequencies contained in the ground plane.|
Obtaining the best performance from analog-to-digital converters (ADCs) has long eluded many circuit designers. One of the main obstacles involves proper grounding. Inadequate grounding techniques in high-speed ADC and mixed-signal circuits and systems can lead to excessive noise when digital return currents find their way into analog circuit areas.
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Obtaining the best performance from analog-to-digital converters (ADCs) has long eluded many circuit designers—so much so that they’ve concluded that the performance claimed in data sheets isn’t possible in practical circuits. One major obstacle to optimizing the performance of ADCs is proper grounding. Inadequate grounding techniques in high-speed ADC and mixed-signal circuits and systems can lead to excessive noise when digital return (ground) currents find their way into analog circuit areas.
There are many ways to configure grounds for ADCs and other mixed-signal products, as well as just as many opinions as to which is the best method. These opinions are generally based on what has been found to be successful. In an earlier article, I discussed the limitations of popular ADC grounding techniques and suggested a split ground plane, which has always yielded excellent first-time noise performance.1 But as good as this method is for obtaining good noise performance from high-speed ADCs, a split ground plane isn’t good for radio-frequency-interference/electromagnetic-interference (RFI/EMI) performance.
Furthermore, as we push ADC and mixed-signal technology to higher speeds and resolutions, we find that the split ground plane no longer works as reliably as it does at lower frequencies. In spite of the grounding problem, there is a way to enhance noise performance while minimizing layout-related radiation. Three concepts dictate how to handle grounding for a combination of good dynamic performance and minimal RFI/EMI: the skin effect, the proximity effect, and a layout that considers these effects.The Skin Effect We know that electrical current always seeks the path of lowest impedance. At relatively low frequencies, this is the same as the path of least resistance. The path of least resistance is where the dc and low-frequency currents fill the entire volume of the conductor. In a plane, then, the current would spread out to fill the entire volume of the plane, and the resistance of that plane depends on its three-dimensional size.
Once the frequency reaches a few megahertz, though, the path of least impedance becomes the path of least inductance. As ac current flows through a conductor, the expanding and collapsing magnetic field around it is strongest at the center of the conductor and weakens with distance from that center. The result is a higher inductance at the center of the conductor that decreases with distance from the center, causing ac to flow primarily near the outside surface of the conductor, or on its skin. This is known as the skin effect.2
The skin effect tells us that at high frequencies, the effective cross-sectional area of the conductor is reduced below the actual full cross-sectional area. So, the ac resistance (real) part of the conductor impedance is greater than we would measure with an ohmmeter. The frequency-dependent ac resistance of a flat conductor (such as a pc-board trace) is defined as:2
Rac = ac resistance in ohms/inch of line length
f = frequency in hertz
ρr = conductor relative resistivity, compared to copper = 1.00
w = flat trace width in inches
h = flat trace height or thickness in inches
If w and h are in centimeters, Rac would be in ohms/cm of line length.
From this formula, we see that at 40 MHz, a typical pc-board trace of 0.006 in. wide by 0.0015 in. high (1-oz copper) would have an ac resistance of 0.11 Ω/in. We can double the cross-sectional area of this trace by doubling the trace thickness. We can also double the trace cross-sectional area by doubling the trace width.
Doubling the trace thickness (height) to 0.003 in. while maintaining the same trace width and surface area would double the volume (cross-sectional area) of the conductor while reducing its ac resistance by 17%. However, doubling the trace width to 0.012 in. while maintaining the original thickness will double the surface area and again increase the trace cross-sectional area by a factor of two. But, the ac resistance is reduced by 44%. We then see that the total surface area of a conductor is more important at higher frequencies than its cross-sectional area.
The skin effect is more prominent as frequency increases, where the conductor may as well be a hollow, thin-walled conductor as far as the current is concerned (Fig. 1). The inductance of the wire or trace causes the current through it to flow primarily on its surface. This will drastically reduce the trace’s effective cross-sectional area and raise the conductor resistance as frequency increases. But this isn’t the only effect upon the ac resistance of a conductor.The Proximity Effect The magnetic field surrounding outgoing and return currents causes those currents to want to flow in close proximity to each other (to minimize the amount of energy required to establish and maintain that magnetic field). This causes the return current in a reference plane to flow through that plane in a path that is as close as possible to its corresponding outgoing current. The result is a flow of return current in the reference plane that is restricted to a narrow area below or above the trace carrying the corresponding outgoing current. The reference-plane current density at any point horizontally displaced from the trace carrying the outgoing current is defined as:3
IRP = the reference-plane current density at horizontal distance D from the outgoing signal trace
i = the outgoing signal current
H = the height of the signal trace above the reference plane
D = the horizontal distance from the edge of the trace
A plot of this formula reveals that reference-plane current falls off rapidly with distance from the edge of the outgoing current trace (Fig. 2). The fact that the return current in a reference plane tends to flow very close to the outgoing current is known as the proximity effect.3
The proximity effect also causes outgoing current to flow mostly on the side or edge of the conductor closest to the return current and the return current to flow mostly on the side or edge of its conductor or plane closest to the outgoing current.
The skin effect and the two cases of the proximity effect (causing reference-plane current to closely follow its corresponding outgoing current and causing current to flow on the side or edge of a conductor nearest its corresponding return current) combine to limit the current-carrying cross-sectional area of a conductor to a very small part of the full cross-sectional area of that conductor (Fig. 3). Because current flows in a small portion of the conductor, the high-frequency ac resistance seen by the current is much higher than we might expect it to be. Although the proximity effect seems to work against us, we will see that we can actually use this effect to our advantage.Radiation Whenever there are two conductors carrying outgoing and return currents, the amount of radiation from those conductors is a function of their separation from each other and of their lengths. Radiation is, therefore, a function of the loop area outlined by the current path. It doesn’t matter whether one or both of these conductors is a piece of wire, a pc-board trace, or a plane. Radiation increases with loop area because of the resulting increase in electromagnetic-field fringing around the conductors. This loop area forms an antenna that will radiate.
An area of copper or other board-plating metal that's grounded at one point can also form a radiating antenna. Energy flowing in the ground plane at that point of connection can be radiated by that surface copper area (Fig. 4). It’s best to either include a grounded via at the other end of the grounded copper or not include this piece of copper at all.
By now, you should be starting to realize that many concepts lay beneath effective pc-board layout design. These concepts, the skin and proximity effects and EMI causes, are our guiding principles when designing layout and grounding schemes. Our goal is to achieve the best noise performance possible while also minimizing RFI/EMI.Performance Needs As mentioned earlier, the skin effect tells us that at high frequencies, current flows on the surface of a conductor, resulting in an ac resistance that is much higher than the dc resistance. We saw that the ac resistance of a typical trace can be about 0.11 Ω/in. at 40 MHz. Assume that the return current in the ground plane sees a resistance of half of this, or 0.055 Ω/in., because of the current spreading out a little from the edges of the outgoing trace. To put this in perspective, current variations as low as 10 mA will cause a noise level of 550 µV/in. of signal travel. A 3-in. distance would then cause a noise level of 1650 µV. Compare this with the LSB size of various ADCs in the Table, which indicates the effects of ground noise with an ac resistance of 0.055 Ω/in. in the ground path and an ADC full-scale input voltage of 2.0 V. This is before the inductance of the ground plane path is considered. Note that lower reference voltages will result in a smaller LSB size and more noise in LSB/in. Note also that this 1650 µV is quite a significant amount of noise for high-resolution ADCs.
The problem with a single ground plane is that digital and analog return currents can flow together. Moreover, the digital return currents tend to have high-frequency content and high amplitude levels. As these digital current flow through the ground plane, they develop voltages across that plane. These voltages can be substantial when compared with the LSB size of high-resolution ADCs.
Noise in the ground plane near the ADC relative to the signal ground point shows up as noise at the input to the ADC. This is because the ground potential at the ADC input is the input reference level for single-ended ADC inputs. Use of differential inputs can greatly reduce the effect upon the conversion result, but to the extent that the ADC input common-mode rejection falls short of 100%, some of this ground plane noise will influence the conversion result. High-frequency common-mode rejection usually isn’t as good as low-frequency common-mode rejection. This noise can limit system noise performance unless careful attention is given to circuit layout.
From this we conclude that it’s important to separate analog and digital ground paths. Hence, we develop the idea of the split ground plane as recommended in Reference 1. Figure 5 shows an example layout using the ADC10321, a 10-bit, 20-Msample/s ADC.
Signal return currents must be allowed to flow in close proximity to their outgoing currents if RFI/EMI is to be minimized. But whenever a line crosses the break in the ground plane, the return current must go around that break to flow through the connection between the analog and digital ground planes. Figure 6 shows the resulting loop area. Such loop areas can radiate, making it difficult to meet RFI/EMI performance requirements. So, we find ourselves providing expensive metal shielding that might be eliminated with a better layout technique. This radiating area may not seem very large, but it’s large enough to radiate high-frequency energy. Remember also that low-frequency digital signals contain harmonic content at much higher frequencies than their fundamental and that power-supply lines can carry signal currents. At the same time, the outgoing current will take a straighter path between the power supply and the component, forming a current loop that can radiate. Obviously, a split ground plane isn’t good if we are to minimize radiation.
To minimize the loop area, we must allow the return currents to find their own path. This leads us to employing a single ground plane. Figure 7 shows an estimation of power-supply current flow with both a solid ground plane and a solid power plane. The digital return currents cause ac voltages to be generated across the ground plane, resulting in digital noise introduced into the ADC. We then face a dilemma. We need a split ground plane to minimize noise, while minimizing RFI/EMI requires a single, unsplit ground plane.
To determine just what is necessary for best overall performance, let’s return to some fundamental principles:
- All currents follow the path of least impedance.
- The impedance of a transmission line is proportional to the distance between conductors.
- The amount of radiation from a signal path increases with the loop area defined by the outgoing and return current paths.
Note that all power to the ADC should be considered analog power. The analog and digital supplies should come from the same source. But, they should be decoupled from each other to prevent contamination of the analog supply by the ADC digital output switching.1 Also, this power source should be the one used for analog circuits and not for digital circuits.Traces Versus Transmission Lines Although all lines are transmission lines, we can generally get away with treating short lines as simple connections. Yet the length beyond which a line must be treated as a transmission line is surprisingly short and is a function of the signal rise time and propagation rate down the board. A line must be treated as a transmission line when its length exceeds that described as:
LMAX is the maximum line length beyond which that line becomes a transmission line
tR is the signal rise time
tPR is the signal propagation rate down the board
Propagation down the trace, tPR, is about 150 ps/in. (6 ps/mm) for a typical FR-4 board. Others use figures between 3 and 4 in place of 6 in the formula above. But I find that relying upon those lower figures can result in marginal designs. A good rule of thumb is that the maximum line length before a line must be considered a transmission line is 1.1 inches per nanosecond of signal rise time.
Of course, a transmission line should always be properly terminated to prevent reflections and standing waves, as these lead to both signal radiation and waveform distortion. Waveform distortion, known in the digital world as signal-integrity issues, can lead to indeterminate timing (jitter) and noise.
Remember that pc-board vias (through holes) are primarily capacitive in nature and present signal-line impedance discontinuities that can lead to reflections and standing waves. This in turn can cause waveform distortion and energy radiation. For this reason, it’s best to avoid vias in signal lines that carry high-frequency signals. When a via is necessary, it’s best that it be near one end of the line or the other. Keep in mind that power-supply traces carry signal-frequency currents.
Having said that, the good news is that impedance discontinuities caused by vias are fairly small and usually not problematic. Even so, it’s best to minimize their use and to avoid them whenever possible.
All lines carrying high-speed signals, analog or digital, have some degree of sensitivity to layout and proper termination. Still, the ADC clock line is almost always the most sensitive, especially with high-speed ADCs. This is because the clock signal determines just when a sample is acquired. Sample-to-sample timing variations show up as noise in the ADC output spectrum.Grounding Open Areas Assuming an internal pc-board layer is the ground plane, it’s common practice to cover all unused areas on the top and bottom of the pc board with grounded copper, called copper fill or copper pour. However, grounding a copper area at a single point creates an antenna that will radiate energy at whatever frequencies are in the ground plane at that point.2 For this reason, you should ground these top and bottom copper areas at more than one point, or don’t cover these areas with copper at all. A look at antenna theory will tell us that we should also avoid floating (unconnected) areas of copper, especially strips.
Large copper areas should have many grounded vias. Small copper areas should be connected to the ground plane at a minimum of two points. If an area is so small that it’s not practical to ground it at two points, copper should be left off that area.Bringing It All Together Many things come into play when it comes to getting the best performance with high-speed ADCs and other mixed-signal components. Knowing the players on the field is the first step toward controlling the situation and getting good circuit performance.
Attention to component placement and power-supply routing makes it possible to achieve low noise performance with high-speed ADCs and other mixed-signal components while providing acceptable RFI/EMI levels. It’s also important to pay attention to the ADC’s clock signal, to the output bus, and to signal conditioning circuitry. Those considerations were discussed in previous articles.1,4,5 National Semiconductor’s ADC Web site (www.national.com/adc) and the National Semiconductor Analog University Web site (www.national.com/analogu) offer information that can help you achieve the performance you expect in your ADC and mixed signal designs.
- "Attack The Noise Gremlins That Plague High-Speed ADCs," Electronic Design, Dec. 17, 1999, p. 107.
- Johnson, Howard and Graham, Martin High-Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), p. 151.
- Johnson, Howard and Graham, Martin High-Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), p. 158.
- "Maintaining Signal Integrity Enhances ADC Circuit Performance," Electronic Design, May 1, 2000, p. 115.
- "Pay Attention To The Clock And Output Bus To Improve High-Speed ADC Designs," Electronic Design, June 26, 2000, p. 137.