DUC Eclipses Competitive Offerings

March 1, 2004
This Digital Upconverter Device Relies On A Unique Patent-Pending Engine Technology To Reduce Power And Costs While Improving Signal-Conditioning Performance.

The cellular-infrastructure market continues to face its own set of challenges. Consider, for example, that the single most expensive component on a base station is the multi-carrier power amplifier (MCPA). Depending on the MCPA architecture and peak-output-power requirements, this device's incremental cost can be anywhere from $300 to $1000/watt.

It's also important to note that CDMA and W-CDMA signals can have more than 12 dB of crest factor (peak-to-average power ratio). But when size goes up, so does cost. Effectively dealing with incoming signals can be difficult enough. But this task becomes all the more daunting when one factors in the reality of today's multi-mode world and the growing anxiety over identifying every opportunity for cost savings and power-output reduction.

Into this quagmire of competing requirements comes Analog Devices. The company stepped in with a new digital upconverter (DUC) that promises to give 3G base-station manufacturers the power and cost savings that they need. At the same time, it significantly optimizes baseband-to-intermediate-frequency (IF) signal conversion (FIG. 1).

This announcement comes as good news to base-station manufacturers. To avoid the output-signal distortion caused by large peaking signals, they previously relied on expensive, highly linear power amplifiers (PAs). Using the AD6633 DUC, those manufacturers now gain access to optimum service, a reduction in power-amplifier requirements, and a power savings of up to 75%.

The AD6633 is a 125-Msample/s, multi-channel DUC. As a member of the VersaCOMM family of products, it upconverts baseband data from a digital signal processor (DSP) to a multicarrier IF signal of a wideband transceiver (FIG. 2). Because it's characterized as a wideband transmit-signal processor, it can operate up to six channels or frequency allocations with built-in user configurability. Optionally, multiple AD6633 devices can be cascaded to synthesize more than six frequency allocations.

One of the defining characteristics of Analog Devices' new device is its patent-pending peak-power-reduction (PPR) engine, which it calls its Versa CREST crest-reduction engine. This engine alleviates the demands that are placed on external power amplifiers. At the same time, it reduces power peaks. Within base-station designs, this engine helps to slash power-amplifier component cost.

The PPR engine limits peaks by creating co-channel destructive interference. The amount of interference that's applied to each frequency allocation is automatically and instantaneously scaled according to the power that's present at that frequency. As a result, operators are free to place powerful and weak carriers in adjacent frequency allocations without disturbing the weaker carriers.

Certain frequency allocations may even request preferential interference allocation. High-speed data channels can therefore enjoy lower error vector magnitudes (EVMs) than the voice channels. Separate power monitors are provided for each frequency allocation as well as the composite signal.

Essentially, the VersaCREST engine enables optimum baseband-to-IF signal conversion by anticipating power peaks earlier in the signal chain. It also can trade crest-factor suppression against signal distortion. In other words, the signal distortions can be allocated dynamically to any individual channel. As a result, operators can configure performance preferences for high-quality data or lower-quality voice communications.

This digital upconverter comprises six independent processing channels and a composite processing block. Each processing channel contains the following: a programmable phase equalizer (for IS-95 applications); a resampling programmable FIR filter; two fixed-coefficient interpolating FIR halfband filters; a fifth-order CIC interpolating filter; and a 32-b full-complex frequency translator. The filter coefficients and translation frequencies are fully independent.

The DUC's composite-processing block works to process the sum of the six processing channels. It includes a 32-tap programmable complex filter, fixed coefficient interpolating filter, and 6-b full-complex frequency translator. The AD6633 also houses an AGC controller and quadrature correction for phase, gain, and offset.

The DUC's patent-pending PPR engine confines the output magnitude to a programmable limit. In a four-channel W-CDMA system, for example, it can reduce peaks by over 6 dB without degrading the adjacent-channel leakage ratio (ACLR). Those reduced peaks result in a lower cost for the associated power amplifier. For large installations, that reduction may amount to thousands of dollars.

The AD6633 device features 18-b parallel output ports and one 20-b input port, which is shared among the six processing channels. It achieves full-complex NCO for 32-b tuning fine resolution and worst spur better than −105 dBc. The DUC also flaunts output automatic gain control, a serial control port, JTAG boundary scan, and user-configurable built-in self test (BIST). The AD6633 requires a 3.3-V input/output and 1.8-V core supplies.

The AD6633 DUC is Analog Devices' first product with crest-reduction technology to target CDMA2000, W-CDMA, and TD-SCDMA 3G wireless-transmitter applications. The converter features an array of programmable wideband channel filters that can be implemented for any of the CDMA2000, W-CDMA, or TD-SCDMA standards. For example, the available filters include all-pass phase equalizer filters for CDMA2000; programmable-RAM coefficient FIR filters; and FIR interpolating filters (two per channel). Complex FIR filters with frequency equalization and fifth-order interpolating CIC filters (one per channel) are available as well.

Thanks to its use of the VersaCREST engine, the AD6633 DUC offers a concrete value proposition. It provides a simplified DUC architecture and decreased overall costs. At the same time, it significantly reduces the performance requirements that are placed on subsequent RF power-amplifier and signal-chain components (FIG. 3). This benefit stems from the DUC's ability to pre-compensate for the image leakage, local oscillator leakage, magnitude roll-off, non-linear phase response, limited signal-to-noise ratio, and power capacity of the RF circuit stages.

The AD6633 digital upconverter is currently sampling. Production quantities will be available in August 2004. In a 196-lead ball-grid-array (BGA) package, the six-channel DUC version is priced at $60.00 per unit in 10,000-piece quantities. The four-channel DUC version costs $40.00 per unit in 10,000-piece quantities.

For complete 3G signal-chain processing, the AD6633 device is best coupled with Analog Devices' AD6654 or AD6636 mixed-signal/digital downconverter and the AD9777 TxDAC+ direct RF upconverter. In addition to 3G wireless-infrastructure applications, the AD6633 is well suited for the general-purpose communications applications in which power crests and system costs present design challenges.

Analog Devices, Inc. 804 Woburn St., Wilmington, MA 01887; (781) 937-1428, FAX: (781) 937-1021, www.analog.com/AD6633.

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