Design A Clock-Distribution Strategy With Confidence

April 27, 2006
Simulation lets you design a transceiver clocking and frequency-planning strategy while making the required tradeoffs between performance and cost.

Clock-distribution devices create multiple copies of a master clock and distribute them to a variety of integrated circuits. They accept single-ended or differential clock inputs and supply multiple single-ended or differential outputs that are divided or delayed versions of the input clock.

A low-phase-noise crystal oscillator (XO) is commonly used to drive clock-distribution devices. Their sinusoidal outputs are then converted to square waves or pulse trains. Clock jitter is caused by statistical variations of the input reference clock and by clock signal processing. Therefore, a phase-locked loop (PLL) often is included to improve output jitter.

A good example of how clock distribution works can be seen in a typical basestation transceiver. In the transceiver, an AD9510 clock-distribution device supplies clocks to components such as analog-to-digital converters (ADCs), digital-toanalog converters (DACs), application-specific integrated circuits-(ASICs), and field-programmable gate arrays (FPGAs), each of which requires a low-jitter clock at a specific frequency and phase. One part of the system may use one logic family, while a different part uses another. Therefore, the clock outputs must support low-voltage differential signaling (LVDS), CMOS, and emitter-coupled-logic (ECL) compatibility.

Of course, the tradeoff between system performance and system cost is one of many challenges faced by transceiver designers. System engineers must decide which components to use in their transceiver design. But generating clocks and distributing them to these components also affects the transceiver's performance.

Figure 1 shows a typical two-carrier W-CDMA transceiver. Complex relationships exist among frequency, phase, and amplitude between the multiple clocks required by the transceiver. Nonetheless, designers still can easily develop a clockdistribution strategy.

On the receiver side, the AD9945 14-bit ADC 2 digitizes a downconverter mixer's output with a 128-MHz intermediate frequency (IF). For optimum performance, the ADC is clocked at 102.40 MHz using a differential LVPECL clock with broadband jitter of less than 300 fs rms. The sampling clock is accoupled via a transformer or capacitors. The ADC output is processed by the AD6636 digital downconverter (DDC), which provides a baseband complex signal from the W-CDMA carrier (I, Q data stream). The DDC requires a 102.40-MHz LVDS clock. This clock is delayed by 0.5 ns relative to the ADC clock. The on-chip multiplier generates a frequency of 128 MHz so that the numerically controlled oscillator (NCO) can frequencytranslate the IF signal to baseband.

The transmitter accepts unfiltered, interleaved I and Q data from two WCDMA carriers. A digital upconverter (AD6633, DUC) performs pulse-shaping, peak-to-average power-ratio reduction (PAPR), and frequency translation of the W-CDMA carriers to a first IF at 19.20 MHz. The DUC requires a 76.80-MHz CMOS clock and outputs complex data at a rate of 76.80 Msamples/s. The ADC and DUC send their output data to an FPGA. The clock-distribution device has an adjustable delay unit, which enables the clock output to be delayed by 0.11 ns to synchronize the transmit path to the observation path. Controlling this synchronization to within 1/64th of the symbol duration allows for sufficient linearization.

The FPGA, clocked at 307.20 MHz, performs digital pre-distortion (DPD). It oversamples the DUC output by a factor of four to generate a complex signal at the same data rate as the ADC. It outputs complex data at a rate of 153.6 Msamples/s, with an IF of 57.60 MHz. This data is the input to the AD9779 dual DAC. The DAC requires a 614.40-MHz clock with a low-jitter differential LVDS drive. Its complex modulation produces a second IF at 96 MHz. Third-order lowpass filters with a 400-MHz, stop-band frequency filter the complex output. The analog filter outputs drive an analog modulator to upconvert from 96 MHz to a radio frequency at 2.1 GHz.

For optimum performance, the 12-bit AD9430 ADC 1 requires a 153.60-MHz differential LVPECL clock with broadband jitter of less than 300 fs rms. It digitizes the downconverted and filtered version of a high-power amplifier (providing the observation path at an IF of 57.60 MHz). This path is critical for accomplishing high-performance digital predistortion. The ADC output is frequency translated to an IF of 19.20 MHz by an NCO built in the FPGA, which supplies a complex signal at a 153.60-Msample/s rate. The 10-bit AD9215 ADC3 monitors the power amplifier's temperature change and feeds it back to adjust the predistortion coefficients. This ADC requires a 30.72-MHz CMOS clock. Finally, a low-jitter (less than 1 ps rms) LVPECL copy of the reference clock is required.

Figure 2 shows the relative delay between the system clock waveforms. Figure 3 shows the spectrum of two WCDMA carriers, centered at 96 MHz from the DAC (a) and 128 MHz from the ADC (b). This example uses the AD9510 eightchannel, 1.2-GHz, clock-distribution IC to demonstrate how system engineers can design the clock-distribution section.

The reference clock is 19.20 MHz. The on-chip PLL synthesizer and external voltage-controlled oscillator (VCO) generate a 614.40-MHz system clock. Eight independent programmable frequency dividers can be programmed to any integer from 1 to 32. Their phaseoffset can add delays in integer multiples of the VCO time period, approximately 1.63 ns in this example. Finally, by taking advantage of the multiple logic families available on this clockdistribution device, the required combination of LVPECL, LVDS, and CMOS clocking output levels for our transceiver is achieved.

Transceiver designers commonly use phase-noise density and timing jitter to define the performance of clocking components. Timing jitter limits the maximum clock frequency in digital systems, the dynamic range of DACs, and the effective number of bits (ENOB) in ADCs. Furthermore, system engineers can estimate the degradation in error vector magnitude (EVM), signal-to-noise ratio (SNR), and bit error rate (BER) that occurs as a result of jitter. This lets them make tradeoffs between the cost and performance of components used in a transceiver. Therefore, calculating the timing jitter at the output of clock-distribution devices is of great interest.

Given the single-side-band (SSB), phasenoise power spectral density S (fm) at a device output, we can calculate the phase noise by integrating Sθ (fm) over the signal bandwidth. We are interested in the broadband noise, and we assume a low integration limit (f1) that's 10 kHz away from the output frequency (FOUT).

The clock-receiver and clock-divider function blocks can have a major impact on the clock distribution device's performance. In the clock receiver, continuous phase noise nφ(t) is limited to the square-wave edges and is aliased to ±FIN. The same aliasing occurs in the dividers and with noise generated inside the clock receiver circuit. See Equation 1 for the rms value (or standard deviation) of the phase noise. This relationship shows that a fixed amount of timing jitter causes higher phase noise at higher frequencies. See Equation 2 for the timing jitter.

Some frequency-divider circuits resample the output signal with respect to the input signal. The divider's output transition is synchronized with its input transition. Thus, jitter occurring on the input will cause the same amount of jitter at the output. As a result, the output phase noise, σ θrms, will be related to the input phase deviation, σ θrms,IN, based on Equation 3, where FOUT and FIN are output and input frequencies, respectively, and N is the division ratio. See Equation 4 for how Equation 2 changes.

Note that the output frequency was divided, so that the timing jitter doesn't change at the divider output. All output drivers with the same signal logic level (LVPECL, LVDS, or CMOS) then will have the same amount of jitter, but the phase-noise density will depend on the division ratio (N) of the output channel. If adjustable delay elements are enabled, the jitter will increase, allowing transceiver designers to trade off between flexibility and timing jitter.

Jitter degrades system performance at the ADCs and DACs. If jitter is present in the sampling clock of an ADC, the sample values are taken either a little too early or a little too late. Similarly, clock jitter at a DAC causes the sample values to be converted to analog at "incorrect" times. The result is waveform distortion and the creation of spurious components related to the jitter frequency.

High-speed, high-resolution ADCs are particularly sensitive to the quality of the sampling clock. Because the track-andhold circuit is essentially a mixer, any noise, distortion, or timing jitter on the clock is combined with the desired signal at the ADC output. SNR degradation caused by aperture jitter (tjitter) at a given full-scale input frequency (fANALOG) can be calculated with Equation 5.

In Equation 5, the rms jitter (tjitter) represents the root-sum square of all jitter sources, including the clock, analog input, and ADC sampling switch. Undersampling applications are particularly sensitive to jitter. Performance in IF-sampling receivers often is limited by clock phase noise, not data-converter performance. This is more apparent in multicarrier receivers. The clock input should be treated as an analog signal in cases where aperture jitter may affect an ADC's dynamic range. To avoid modulating the clock signal with digital noise, the power supply for the clock drivers should be separated from the power supply for the ADC outputs.

In the above system, clock planning can be simulated with ADIsimCLK. With this tool, users can create custom references and VCOs, or choose from a library of devices available from major manufacturers. By starting with highperformance custom oscillators, users can determine the baseline jitter limitation of the on-chip PLL and the clockdistribution circuitry. Users then can modify the phase noise of the reference and VCO to see the impact on output phase noise and jitter.

DESIGNING A LOOP FILTER The VCO's phase noise significantly impacts system performance, because it typically dominates the phase noise of the clock-distribution outputs at offset frequencies outside the PLL loop bandwidth. The broadband phase-noise floor generally dominates timing jitter introduced by the VCO. With the help of a simulation tool, it's possible to design a loop filter for the on-chip PLL that achieves jitter performance that's consistent with component specifications. The effect of loop bandwidth on the output phase noise/timing jitter depends on the phase noise of the VCO and reference oscillator. For this example, we choose a Sirenza VCO (VCO190-630T), an Epson-Toyocom crystal oscillator (TG-5001LA), a 10-kHz target bandwidth, and a 45° phase margin.

The VCO tuning voltage impacts the type of loop filter needed. For the simplest designs with a passive loop filter, the VCO tuning voltage must be compatible with the voltage required by the charge pump. The clock-distribution device has an external supply pin to the charge pump (VCP) so the charge pump voltage can be higher than the logic voltage for the rest of the chip, enabling greater range when active filters are used. The ADIsimCLK simulation tool designs the PLL to achieve a specified loop bandwidth and phase margin, calculates the exact component values for the loop filter, and performs all analyses with these values. Users can build the loop filter with industry-standard component values and see how this performance varies with component parameter tolerances.

Clock-simulation tools give transceiver designers access to information on termination options and phase-noise density. For example, consider the OUT3 clock of Figure 1. The simulation tool yields an estimation of signaltonoise-ratio (SNR) degradation due to the combination of IF selection and timing clock jitter of a clock-distribution device. It also displays various plots and calculates the ADC's SNR and effective number of bits (ENOB) versus IF (Fig. 4).

Given the required dynamic range, users can calculate the ADC resolution that's needed for an IF-sampling architecture. Users also can investigate the phase-noise performance required for the clock-distribution device to comply with certain air-interface BER specifications. This can be accomplished by modifying the frequency planning ( intermediate frequency), VCO, and loop filter in the simulation tool. With the help of a simulation tool, users can estimate the phase noise of an ADC's sampling clock.

To add precision to Equation 5, we must include SNR degradation due to quantization noise, differential nonlinearity (DNL), and thermal noise. All of these terms are combined into one additional term in Equation 6. M is the number of bits and is composite rms DNL in LSBs including thermal noise.

Then, based on adjacent-channel selectivity tests, transceiver designers can estimate the effect of reciprocal mixing of a sampling clock when a stronger signal is near in frequency to the desired weaker signal. The adjacent channel will be mixed with the phasenoise floor of the sampling clock, and it will appear as noise within the desired weak signal at the ADC output.

Using a simulation tool lets transceiver-designers design a clocking and frequencyplanning strategy without having any ICs on hand. It helps them make necessary tradeoffs between performance and cost for their transceiver components.

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