ADC clock gating circuit maximizes data throughput

May 1, 1998
When reading the data from a serial analog-to-digital converter (ADC), it may be desirable to use a serial port available on a microprocessor or a digital signal processor. If the ADC offers high resolution (i.e., 16 bits or greater), it may actually...

When reading the data from a serial analog-to-digital converter (ADC), it may be desirable to use a serial port available on a microprocessor or a digital signal processor. If the ADC offers high resolution (i.e., 16 bits or greater), it may actually degrade the converter’s performance by having the microprocessor’s serial data clock running at the same time the ADC performs a conversion. Or, more specifically, during the last half of the conversion when the least significant bits are being determined.

The ADC’s specifications that could be degraded are integral nonlinearity, differential nonlinearity, or transition noise. Unfortunately, some serial ports found on commercial processors will generate a data clock that continually runs even when data isn’t being read from the ADC. Therefore, the clock can’t readily be shut down during the analog-to-digital conversion cycle.

This circuit will take a continuous clock provided by the serial port, pass the minimum amount of clock pulses required by the ADC on through to the converter and block all of the other clock pulses. This will minimize the effect of digital feedthrough of the clock during the sensitive portions of the ADC’s conversion period. The circuit shown in the figure is designed to read the data from the ADC’s previous conversion cycle during the first half of the current conversion cycle. This method of reading the data is ideal for maximizing data throughput, assuming the ADC isn’t sensitive to having its serial data and clock pins changing state during this first half of the conversion.

A signal from the ADC that indicates when the converter is performing a conversion is required by the circuit. In this illustration, the ADC is providing the signal BUSY_B, which is Low during the period of time the conversion is occurring. This circuit assumes the ADC presents data on the rising edge of SCLK, and the serial port will latch the data on the subsequent falling edges of SCLK. The circuit is held in a reset state while BUSY_B is High by forcing the binary counter to preload all zeros. This will also force its ripple carry output to High. With BUSY_B High, the receive frame sync signal to the serial port, RFS_B, is forced High and the clock signals are blocked at U6 and unable to pass through to the ADC.

When BUSY_B goes Low to indicate the start of a conversion cycle, the binary counter is taken out of the preload state and will begin counting up with each falling edge of SCLK from the serial port. On the 16th rising edge of SCLK, after BUSY_B goes Low, the ripple carry output from U3 will go Low. On the subsequent falling edge of SCLK, the 16th falling edge after BUSY_B went Low, the ripple carry output will return High. This rising edge of the ripple carry out will clock U4 and force its Q output Low. When U4-Q goes Low, it forces U5 to block any further clock pulses from passing through to the ADC.

The clocking of U4 also removes the receive frame sync to the serial port. The clock pulses to the ADC will remain blocked for the remainder of the time that BUSY_B is Low. When the analog-to-digital conversion is complete, BUSY_B will return High and the next failing edge of SCLK will force the counter into the preload state again.

Assuming the ADC is more sensitive to digital feedthrough when the least significant bits are being determined, all 16 data bits must be read before this point of sensitivity occurs. This will place a lower limit on the frequency of SCLK. If a converter with a conversion time of 5 µs is used, for example, the frequency of SCLK should be set to 8 MHz to ensure that all 16 bits of data can be read in a time less than the first half of the conversion cycle. An 8 MHz clock has a period of 62.5 ns from rising edge to failing edge and, therefore, the worst-case propagation delay through this circuit would have to be less than this value.

By reversing the connections at the outputs of flip-flop U2, the circuit operation can be modified so that the data from the ADC would be read immediately after a conversion is complete rather than after the conversion begins. Reading the data after the conversion is complete will, however, result in a lower data throughput.

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