Mixed-signal design isn’t new. But as designs continue to get larger and more complex, with ever increasing amounts of digital and analog content, design implementation is getting more challenging. Traditional physical implementation methodologies are failing to provide efficient solutions for these advanced mixed-signal products, prompting new requirements that will be necessary for future generations of designs.
The oldest mixed-signal designs included larger amounts of analog functionality and relatively smaller amounts of digital control logic. Often referred to as A/d (big “A,” little “d”) designs, they are used in interface applications to monitor and feed back analog performance information, like tire pressure and fluid level monitors in automotive applications. These A/d designs are created using a custom methodology, where logic functionality is captured in drawn schematics and then implemented in custom layout environments.
As pure digital design teams added peripheral analog functionality, these designs became known as D/a (big “D” little “a”) designs. Examples of such designs can also be seen in automotive applications, such as the processor used to control the main radio/navigation/climate management interface. Because of their relatively large sizes, D/a designs are mostly created using a more automated methodology, where a Verilog netlist describes the logic functionality and then the physical layout is created using a cell-based, timing-driven ASIC methodology.
Mixed-Signal Design Challenges
Advancing process technologies continually allow design teams to integrate more functionality on the same chip, creating larger mixed-signal system-on-a-chip (SoC) designs that will stretch and eventually break traditional design methodologies. These complex designs could evolve from increasing the digital content within A/d designs or by adding significantly larger analog components to large D/a designs.
Separate analog and digital design teams always create large mixed-signal SoC designs. These teams need optimized environments to help them most efficiently create their component parts. However, there are stages of the flow where it is critically important for these teams to efficiently work together. Good team coordination is required during the floorplanning and chip-assembly stages, when either team or both teams may need to make changes based on top-level verification and analysis.
As designs get larger, the trend will be to create them using more hierarchical techniques, where much of the required analog and digital intellectual property (IP) is created in parallel by multiple design teams. This is different from existing methodologies that import hardened IP with fixed functionality, size, and pin locations.
In addition to efficiently managing the increasing design sizes, the designs themselves are getting more complex, with an increasing number of analog-digital-analog interfaces and operating modes that must be accurately implemented and validated. The floorplan itself can become critical in determining the success of a project, where tradeoffs between die size and ease of implementation often are made.
Too aggressive a die size can easily result in extremely challenging, maybe impossible, implementation. Functional verification techniques that have been successfully used in the past could break with the increased design sizes, unless attention is paid to establish efficient, hierarchical verification approaches.
Engineering change orders (ECOs) are a fact of life, so the solution must be able to accommodate a range of ECOs, from those that require manual, interactive approaches to those that require fully automated fixing. A number of mixed-signal design teams have stated that improvements in floor-planning and ECO management alone could result in implementation schedule savings up to 25%, which is a tremendous cost saving!
Mixed-Signal Implementation Solution Requirements
Any advanced mixed-signal implementation solution must enable efficient and automated floorplan-to-signoff implementation of the most complex mixed-signal designs. A high-level suite of requirements that enable such a solution includes floorplanning, physical implementation, ECO management, design closure, and ease of use.
The A and D teams both control and drive the floorplanning. These teams must be able to create and rate multiple floorplan options. They also need to be able to handle and optimize “soft” blocks, where shape, size, and pin locations aren’t yet fixed. Floorplanning enables the rapid prototyping of a design and creates the constraints that help guide implementation.
These constraints drive physical implementation. During this stage, designers can optimize environments for efficiency manually and interactively for analog design and via automated place and route for digital design. Physical implementation also supports low-power digital implementation and full suites of analysis for advanced process technologies.
The design process should be flexible so ECOs can be managed in an optimal fashion. This means manual and interactive processes for the most critical analog problems. It also means automated processes to address Verilog input changes.
Design closure requires functional verification for complex A-D interfaces, including post-route parasitic loading. It additionally requires comprehensive digital timing closure and signoff using static timing analysis (STA) as well as comprehensive full-chip power and power integrity analysis and signoff.
Ease-of-use means improved interoperability between A and D design implementation environments. It should involve a single design database to enable information sharing in addition to the consistent use of constraints.
The demand for advanced mixed-signal designs continues to grow, driven by wireless, automotive, computer, and communication applications and enabled by advanced process technologies. Mixed-signal design teams are struggling to create advanced designs using traditional implementation methodologies that cannot efficiently manage such design complexity.
A new, more advanced mixed-signal implementation solution is required to meet the growing demand. The solution must enable efficient and optimized design implementation, including custom and fully automated design methodologies, and enabling advanced low-power digital design methodologies for power-sensitive applications. The implementation solution must also drive full-chip design verification and signoff analysis to ensure good quality of silicon.