One-transistor, one-capacitor (1T-1C) DRAM cells have been commercially implemented since at least 1999. They save die area compared to conventional 6-T DRAM cells, use less power, yield better, and exhibit faster access times. Unfortunately, the storage-capacitor element of the cell presents scaling difficulties below 100 nm.
According to the International Technology Roadmap for Semiconductors (ITRS), "Since the DRAM storage capacitor gets physically smaller with scaling, the EOT \[equivalent oxide thickness\] must scale sharply...dielectric materials having high relative dielectric constant will be needed.... All in all, maintaining sufficient storage capacitance will pose an increasingly difficult requirement for continued scaling of DRAM devices."
It's been said that negotiations between Honeywell and Cypress were dragging until Cypress president T.J. Rodgers came upon a technical paper describing SOI as the salvation of the 1-T DRAM. That story makes a certain amount of sense. At CICC in 2002, Pierre C. Fazan (Innovative Silicon Solutions) and Serguei Okhonin, Mikhail Nagoga, and Jean-Michel Sallese (Swiss Federal Institute of Technology) presented a paper called "A Simple 1-Transistor Capacitor-Less Memory Cell for High-Performance DRAMs," which announced development of a one-transistor DRAM cell that used SOI's floating body effect to eliminate the capacitor.
To store a binary 1 in these N-MOSFET 1-T cells, a positive drain voltage pulse creates an excess positive charge in the device body via the impact-ionization mechanism. This increases the channel current. To store a binary 0, positive drain and gate voltage pulses create an excess negative charge in the body by removing holes, which decreases Ids.
Reading is accomplished during refresh by comparing channel current in the cell with the current in a reference cell. Reads made at low drain voltages won't affect the states of the read cell or the reference cell, and reading during refresh interval doesn't disturb the stored information.