Audio IC supplier Wolfson Microelectronics of the U.K., partnered with Japan's Sanyo, is prepping a mixed-signal device for next-generation automotive entertainment systems. This audio chip will tap advances in the state-of-the-art 0.18-µm CMOS process to integrate a high-speed analog-to-digital converter (ADC) with a high-performance DSP on one die.
The IF ADC in this design is a 14-bit, 10-MHz pipe-lined subranging converter that flaunts 80-dB spurious-free dynamic range (SFDR), 70-dB total harmonic distortion (THD), and 200-MHz analog input bandwidth. Using 0.18-µm CMOS, it will be integrated on one chip with a 100-MIPS, 24-bit, fixed-point programmable DSP that has over 100 kgates (see the figure).
The first silicon from this joint effort is expected to be realized by the middle of the third quarter. To get it right the first time, the partners are tackling several process and design issues up front. Most notable is the coupling of noise from high-speed digital circuits to analog circuits, as well as reduced signal dynamic range due to lower supply voltages.
Noise from high-speed circuits is normally coupled to low-level analog circuits via references, substrate, and ground. Designers are implementing several techniques to curb noise. Besides using differential topology, careful layout, and on- and off-chip decoupling, Wolfson is using triple-well isolation to keep most sensitive analog circuitry physically separate from the digital circuits. The designers also are combining differential techniques with sample and hold circuitry, an input driver, and a pipelined subranging architecture.
Simply refining the process and improving the architecture is not enough. Optimized, accurate models are needed to guarantee results in the first silicon. As a result, Wolfson has developed new proprietary simulation models from scratch for the deep-submicron CMOS process. The new circuit-level models simulate physical coupling paths and parasitic elements. These include substrate and interconnect parasitics, junction capacitances, and package inductances.
While this design's digital circuits will operate on a 1.8-V supply, a 3.3-V supply will power the analog circuits. The clock frequency for the DSP is 100 MHz. It incorporates a 16k RAM. Ultimately, Wolfson intends to combine this high-speed signal-processing chip with a 0.35-µm CMOS-based mixed-signal audio processor in a multichip module. The plan is to deliver a total audio solution to next-generation automotive entertainment systems.
Visit www.wolfsonmicro.com for further information.