Design A High-Resolution Δ-Σ ADC Using An 8-Bit Microcontroller

July 24, 2000
A simple integrating amplifier is combined with an MCU's analog peripherals to realize a 10-bit analog-to-digital converter.

There are numerous methods of implementing delta-sigma (Δ−Σ) analog-to-digital converters (ADCs), and each has its own set of advantages and disadvantages. Some engineers employ complex systems to solve simple conversion problems, while others exploit simple circuits to handle difficult tasks. A deeper analysis of the basic circuit, however, can lead to some interesting low-cost alternatives. The fundamental Δ−Σ ADC model, described in this article, is an inexpensive design strategy. It requires a simple integrating amplifier and a microcontroller's analog peripherals to create a high-resolution converter.

In this scheme, the conversion from analog to digital is performed with the internal-voltage reference, comparator, and two counters in the 8-bit microcontroller. These internal-microcontroller analog peripherals, along with the external integrator, are used to complete the implementation of a first-order modulator. This modulator is then combined with an output-digital filter, which also is implemented in the microcontroller unit, to complete the design. Consequently, the only components external to the microcontroller are an op amp, two resistors, and a capacitor.

Until now, the microcontroller alone wasn't able to handle the Δ−Σ function, except for the digital-filter block. But, the recent addition of analog cells to the controller's silicon makes such an integrated solution possible.

Basically, the Δ−Σ ADC can be simply modeled with a modulator and a digital filter (Fig. 1). The modulator part of this ADC integrates an input signal, so its output passes a threshold voltage established with a comparator and a voltage reference. Within the modulator, the analog-input signal is subtracted from the output of a 1-bit digital-to-analog converter (DAC). The DAC converter is part of the negative feedback loop. This differenced signal is converted by the integrator to a voltage that ramps from negative to positive or positive to negative, depending on the output of the difference amplifier.

This ramp is presented to one of the two inputs of a comparator. When the output of the integrator passes the reference voltage of the comparator, the output of the comparator toggles between high and low. On a regular time schedule, that output is fed back to the difference amplifier via the 1-bit DAC. Additionally, the output of the comparator is fed forward to a digital filter. With time, the output of the digital filter provides a multibit conversion result. This basic design topology has been used to create myriad Δ−Σ-based converters that provide high resolution for very small signals, such as those from a bridge sensor. Still, the challenge is implementing the modulator in a microcontroller.

The circuit in Figure 2 implements such a classical first-order Δ−Σ ADC using a single-supply CMOS operational amplifier, RC network, and an 8-bit PIC16C622 MCU. In this design, the integrator is implemented with the capacitor CINT. The current through R1 is generated by VIN and the current through R2 is generated by VRA3. These provide the currents that charge the CINT. Their combination charge or discharge CINT to the point where the comparator output is toggled. By driving RA3 in accordance with the output of the comparator, C1OUT, the 1-bit DAC can be implemented in firmware. At the same time, the digital filter can be realized with two counters, along with a simple averaging algorithm in firmware.

The absolute accuracy of this integrating capacitor isn't critical, but its stability from integration to integration is important. Because the capacitor voltage is held at a constant level in this circuit, the dielectric absorption of the capacitor isn't an issue. In this example, the maximum-voltage deviation due to the nonlinearity of the RC network is about 8 mV. If the RC time constant of the circuit is greater than the sample frequency, then the logarithmic nature of the time response will cause linearity errors in the system. The RC time-constant linearity error is minimized with:

tRC = R1 || R2 × CINT
tRC ≤ tSAMPLE /10 (for good linearity)

Capacitor leakage errors also will contribute to the system's overall error. The capacitor types that have appreciable leakage are the electrolytic ones. These include aluminum and tantalum, which shouldn't be used in this circuit. A capacitor type that fits well is the NPO ceramic type, due to its lower cost, smaller size, better stability, and wider range of values.

When VRA3 of the microcontroller is set high, the voltage at RA0 ramps up until the output of the comparator is triggered low. With the change in the comparator output, the driver to the RA3 output is switched from high to low. With the potential at RA3 low, the capacitor starts to discharge, thereby causing the voltage at the input to the comparator (RA0) to decrease. The status of the output of RA3 remains low until the comparator is tripped high. Change in comparator output is clocked to the output of RA3 by the microcontroller.

The ratio of R1 and R2, with respect to the input-voltage range, are selected using the following formulas:

VIN(P−P) = VRA3(P−P) × (R1/R2)

where: VIN(CM) = \[(VIN(MAX) − VIN(MIN))/2 + VIN(MIN)\]

VREF is the voltage applied at the comparator's noninverting input. This voltage can be supplied internally by the microcontroller, or externally through the reference pin RA0.

VRA3(P−P) = (VRA3(MAX) − VRA3(MIN))

The low-offset, 25-µA MCP606 CMOS op amp driving R1 is used to isolate errors that would be caused by the source impedance of the input signal. The op amp's offset voltage is 250 µV at room temperature.

During the time that the modulator section of the circuit is cycling, two counters are used to keep track of the time,"Counter," and the total number of times that the comparator is high, "Result" (Fig. 2 again). The flow chart labeled DelSigA2D shows the algorithm employed to implement such a concept (Fig. 3).

When a conversion isn't in process, the output of the comparator is directly connected to RA3. This keeps the voltage at RA0 equal to the reference voltage of the comparator. When function DeltaSigA2D is called to perform a conversion, the result and counter variables are cleared (see the Code Listing). Then, the comparator output is put under active program control.

The microcontroller program checks the output of the comparator at the beginning of each loop. If the voltage on the capacitor is less than the reference voltage (VRA2), then the voltage at RA3 is set high. This injects charge onto the capacitor, CINT, which increases the voltage at VRA0. If the voltage on the capacitor is greater than the comparator's reference voltage, RA3 is set low, which removes the charge from the top of the capacitor. When the voltage at RA0 is greater than the voltage at RA2, the result register is incremented.

After this firmware decision, the counter register is incremented. This continues for as long as it's necessary to achieve the required resolution. For instance, ten bits of resolution requires 210 (1024) times through the loop. Each lap through the loop takes 17 instruction cycles. Additional no-operation (NOP) instructions are used to keep all paths through the code equal. Upon completion, the comparator output is fed directly to RA3, and the conversion is sent to output registers. If a PIC16C622 is used in this circuit with a 4-MHz clock, then the integration cycle will be 20 µs. At this rate, the 10-bit conversion will take 20.48 ms.

Test data for this circuit shows that the maximum-code error was ±2 counts, or 2 bits of uncertainty. Consequently, the effective number of bits in this ADC is 8 bits p-p (Fig. 4). This resolution can be improved by increasing the number of conversions and using digital filtering following these conversions.

Typically, a sensor that's configured as a Wheatstone bridge outputs a low-level differential signal. The design challenge for this type of a sensor is to capture these small signals and convert them into a digital format that provides an 8- to 12-bit representation. A circuit designed to capture these low-level voltages is depicted in Figure 5.

The analog portion of this circuit consists of the bridge sensor, an analog multiplexer, an amplifier, and an RC network. The sensor that's selected for this example is a load cell. The rated output of the load cell is equal to 2 mV/V. When the bridge is excited with 5 V, the maximum-nominal output swing is equal to ±10 mV. A complete list of the load cell's specifications is provided by Table 1. The analog multiplexer is used to switch the two outputs of the sensor into the single-ended modulator. An amplifier configured as a buffer is used to isolate the sensor load from the modulator's RC network. This network implements the integrator function of a first order modulator.

The basic operation of this circuit is the same as the previous circuit with the exception of the multiplexer at the input. With this added feature, the two outputs of the Wheatstone bridge are alternately switched into the signal path after the counter register reaches 1024. The two results from these cycles are subtracted to give the conversion results. This technique provides 10 bits of resolution with 9.9 bits of accuracy (rms). Again, the design equations for this circuit are:

VIN (P−P) = VRA3 (P−P) × (R1/R2)


VIN (CM) ≈ VDD/2, or (VLC+ + VLC−)/2

where VREF is the voltage reference applied to the comparator's noninverting input and is approximately VSENSOR/2. If it's made external, this reference voltage can be used to adjust offset errors. Again:

VIN (P−P) = (VLC+(MAX) − VLC(MIN)),

or (VLC+(MIN) − VLC−(MAX)), which equals the sensor's full scale range, and:

VRA3 (PK− PK) = (VRA3 (MAX) − VRA3 (MIN))

The offset and gain are the dominant types of errors that the bridge and signal-conditioning path produces. Bridge sensor circuits also produce other errors, such as linearity, noise, hysteresis, repeatability, stability, and aging. But, these topics are beyond the scope of this article.

Mathematically, the offset error of a system can be described using the generic formula out = a + bx, where a is the offset error, b is the span or gain of the system, and x is the input to the system. In this equation, the offset error is described with a constant additive to the entire transfer function. The offset error is typically measured when the input signal is zero. This technique provides an output signal that's equal to the offset. The offset error can originate at the sensor or within the various components in the analog-signal path. This error is repeatable and stable unless the operating conditions—such as temperature, voltage excitation, or current excitation—change.

The offset errors in the circuit shown in Figure 5 come from the load cell, the operational amplifier (A1), the port leakage current at RA0, the comparator's voltage reference (VREF), the comparator offset, and the nonsymmetrical output port of RA3. Half of the bridge-offset error is seen on the two output terminals of the bridge. Because the signal path for the two outputs of the sensor to the microcontroller are the same, the conversion data taken from the positive leg of the load-cell sensor (LC+) has the same signal-path offset and gain errors as the conversion data taken from the negative output of the load-cell sensor (LC−).

To accommodate these errors, the design equations for the circuit remain:

VIN(P-P) = VRA3 (P−P) × (R1 / R2)

But, now the worst case variation is:


where LCOFFSET is the maximum-offset voltage that can be generated by the load-cell bridge, A1OFFSET is the offset voltage of the op amp, and RA0OFFSET is the offset error caused by the leakage current of port RA0. This leakage current is specified at 1 nA at room temperature and 0.5 µA (max) over temperature. Plus, it causes a voltage drop across the parallel combination of R1 and R2. VREF(OFFSET) is the offset error of the internal voltage reference of the microcontroller. This error can be reduced significantly with an external voltage reference. Likewise, C1OFFSET is the offset of the internal comparator of the microcontroller and RA3OFFSET is caused by the inability of RA3 to go completely to the rails. It can be quantified by RA3OFFSET = \[(VDD − RA3HIGH) − RA3LOW\] /2. This formula assumes VREF = VDD / 2. The maximum magnitudes of these errors are summarized in Table 2.

The resulting offset errors are added to the differential-output voltage of the load cell. As a result, the output voltage for this system can be written as:


which simplifies to:


Given the design equations for this circuit and the errors in Table 2, the total expected offset error over temperature for the electronics is 67.8 mV. With a sensor full-scale range of ±10 mV, the dynamic range of the system would be approximately 7.8 times larger than the nominal, error-free peak-to-peak range at the input of the comparator.

The 1-kΩ potentiometer with its wiper connected to RA0 is placed in series between the power supply (5 V) with two 10-kΩ, 1% resistors (Fig. 5 again). This configuration provides a voltage-reference range to the comparator of ±119 mV centered around midsupply. If an external reference is used with a ±0.5-mV error range, the electronics will contribute ±19.3-mV offset error over temperature. This changes the worst-case full-scale peak-to-peak range of the system to ±29.3 mV. This is only approximately three times larger than the nominal full-scale output (±10 mV) of the sensor.

Offset errors of the circuit can be calibrated in firmware. This is performed by subtracting the conversion code results of LC+ from the results LC-. Firmware calibration is an efficient way to eliminate most of the offset errors. The tradeoff, however, for having offset adjustments performed by the microcontroller is dynamic range. In anticipation of these offset errors, the designer should increase the peak-to-peak analog-input range of the conversion system. While this will result in a conversion that has a wider dynamic range, the accuracy of the system will be lower.

The span or gain of a system can be mathematically described as a constant, which is multiplied against the input signal. A system with a gain error deviates from the ideal, as described in the formula below:

Actual output = Input × Ideal gain (1 + Gain error)

For this circuit, the span errors are less influential than the offset errors. Additionally in Figure 5, the system span errors of the circuit originate in the load cell (±20%), the resistors (±1%), capacitor (±10%), and the on-resistance of the RA3 port (0.2%).

Span errors can be effectively removed in the analog domain. For instance, the span error of the sensor can be adjusted with the sensor's excitation voltage. As a tradeoff for this adjustment strategy, the common mode voltage of the sensor is changed, which creates offset errors with respect to the reference voltage (VREF) of the comparator. This problem can be alleviated by making the voltage reference ratiometric to the sensor excitation source. Span errors also can be adjusted with either R1 or R2. A potentiometer is used to perform this function. This type of adjustment doesn't change the offset error of the system. The circuit is able to rely on firmware calibration with a reduction in the dynamic range of the system.

In reality, an alternative circuit has been proposed to perform the analog-to-digital conversion for slow-moving signals from sensors. This alternative is a low-cost and low-part-count solution that gives a high degree of resolution when the power of the microcontroller is used to implement digital filtering.

Recommended Reading:

Baker, Bonnie C., "Anti-aliasing, Analog Filters For Data-Acquisition Systems," AN699, Microchip Technology Inc.

Morrison, Ralph, Noise and Other Interfering Signals, John Wiley & Sons Inc., 1992.


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