In the rush to deliver broadband services through the installed copper infrastructure, it becomes critical to accurately assess the true trade-offs in the line-driver design. Starting from the required line power and crest factor, a simple analysis will give the required output amplifier voltage and current requirements as a function of the transformer turns ratio going out onto the line. Optimizing the design then requires an assessment of the internal driver power dissipation and harmonic distortion.
This optimization is done as the driver operating point is adjusted to meet the varying peak load voltage and current requirements versus the turns ratio. Once the basic driver design is set, other features, like an active filter, can be added to the driver.
In any line-driver design, the most fundamental starting point is the voltage that must be delivered onto the line. In the alphabet soup of DSL, the specific modulations, target BER, and frequency allocations for each version are hotly debated issues that strongly influence the line-voltage requirements. For a general-purpose line-driver discussion, we'll assume that the targets are given by the application. The importance of these assumptions, however, will be clearly illustrated in the driver internal power calculations. The minimal specifications required to start the line-driver design are:
- Average power level required on the line (PL)
- Crest factor for the modulation chosen (CF)
- Line impedance assumed for the average power specification
- Transmission frequency band
- Target harmonic distortion specifications
The first three of these may be used to compute the initial requirements for any line driver, which at a minimum, must deliver both the required voltage and current output swing at the peaks. Once this most basic requirement is met, the designer may consider the additional signal performance issues (principally associated with harmonic distortion and power efficiency).
The maximum required line voltage, VPP, may be computed by stepping through the following equations:
Here, PL is the specified average line power developed from the power spectral density mask being considered; RL is the assumed line impedance; and CF = VP/VRMS.
The first equation is solved for VRMS. Then, CF is used to calculate the maximum desired VPP on the line. PL is typically given in dBm, but it may be converted to watts using PAVG = (0.001)*10(PL/10). The line power in dBm will be referred to as PL, while PAVG will represent average line power in watts.
The example calculation shown is a typical upstream transmission requirement for full-power, DMT-based ADSL where the frequency band is in the 30- to 138-kHz region (see the table). Because most xDSL applications use asymmetric data rates, the upstream frequency band for FDM systems usually goes below the downstream band. This way, it experiences less attenuation, permitting a lower-power transmitter on the customer side. The principles described here apply to either side, but the examples will focus on the lower-power upstream (or CPE or ATU-R) side.
The CF strongly influences the driver's power dissipation. Called the peak-to-average ratio (PAR), this is set by the modulation scheme chosen and limited by the DSP. PAR is related to CF by CF = 10(PAR/20). The Issue 1 and 2 T1.413 ADSL standard specifies a PAR of 15 dB, which translates to a CF of 5.6, very close to the more common 5.33 (see the table, again).1
A higher CF will always dissipate more power in the line driver. That's because the higher peak-output-voltage excursions require a higher supply voltage, which will require a higher quiescent power. In almost all cases, the actual power delivered out onto the line from the power supplies (through the driver) is very small compared to the total power dissipated by the line driver internally.
The maximum VPP on the line may be taken as a fixed design goal (referred to as VLPP). For a given VLPP and impedance, the amplifier's output voltage and current can be traded off with the line transformer's turns ratio. As a result, one can obtain the total VPP across two amplifier outputs and their peak output currents with the transformer turns ratio (n) as a variable (Fig. 1).
The two amplifiers form a push/pull output stage through impedance matching resistors into a transformer. The resistors ensure a line match on the output side of the transformer and limit fault currents, but they will dissipate half the total power delivered at the output. The desired line power accounts for the other half.
Once VLPP is known, the designer can use the transformer turns ratio to trade off the required voltage and current out of the amplifier. This allows different types of amplifiers over a range of supply voltages to be considered for a particular requirement. The transformer turns ratio forms a primary design variable that will determine the required amplifier output voltage and current. Increasing the turns ratio will decrease the required voltage swing, but at the expense of a higher current output. Moreover, increasing the turns ratio will allow a lower power-supply voltage and, in turn, use of low-voltage components.
There are limitations, however, to how high the turns ratio can go. For instance:
- High peak-output currents will start to limit the available output- voltage swing in a driver due to internal voltage drops. This mainly impacts the power efficiency if the supply voltage is to be optimized.
- A high turns ratio in transformers can limit bandwidth and be more prone to distortion.
- Often, the transformer is in the path of the received signal path coming down the line. If so, a high step-up ratio going out onto the line for the driver will mean a high step-down for the receive signal. This can start to impact noise and, hence, reach. Turns ratios up to four can be considered, but most systems work best at two or lower.
The last point touches on another aspect of the line-interface design: the line receiver. This will not be discussed here in any detail, but even at low turns ratios, it's critical to use a low-noise amplifier. A dual op amp like the OPA2680 with 4.5-nV/√—Hz input voltage noise and a very flexible voltage feedback design can meet most input receiver requirements.
With this push/pull arrangement, the designer must keep track of the required voltages and currents at each amplifier output. The voltages must be exactly 180° out of phase with each other. Given a total required VPP equal to 2VLPP/n across the two amplifier outputs, each side must deliver one-half of the total swing. However, the peak current (IP) flowing out of one amplifier flows into the other (and vice versa). So IP, which is bipolar, is actually only one-half of the total peak-to-peak current. IP is:
Considering just the output voltage swing on one side, it would initially appear to see a total load impedance of 4R equal to 2RL/n2 when the line load is reflected through to the primary side of the transformer (remember, 2R = RL/n2). Still, since whatever voltage is being applied by one output is being doubled by the other going in the opposite direction, the apparent load to each output is actually half this value, or 2R. When evaluating the output requirements of each amplifier, it's often this 2R load that's used as the equivalent load impedance (particularly for distortion purposes).
The first key question for the drive amplifier is: As the turns ratio is increased (requiring less voltage but more current out of each amplifier), what power-supply voltages are required to ensure that the maximum swing can be delivered without clipping? This analysis may be used to find the design point that meets a target power-supply requirement (either driven by the system targets or parts capability), as well as to evaluate power efficiency.
Every amplifier has a no-load output voltage headroom for linear operation, although it may not be the same for positive and negative swings. The output stage also will have a finite impedance from the power-supply voltages to the output pin. This also will decrease the available output-voltage swing as more current is required from the output stage.
A simplified model for an output stage can include individual transistors that are considered ideal, but have a voltage source and resistor to the power supplies at their collectors or drains (Fig. 2). The voltage sources (V1 and V2) model the no-load headroom required for linear operation, while the resistors model the decrease in output swing available as more load current is required.
For analysis purposes, these voltages may be increased from the actual no-load output-voltage swing to provide additional linear operation guardband. For now, though, the model is a single-supply design with the load tied to a supply midpoint to model the bipolar output-current characteristic. But the analysis applies to dual-supply designs as well.
The easiest way to get to a result in this case is to assume a power-supply voltage and compute the maximum available output, VPP, for given values for V1, V2, R1, and R2. The key is to recognize that one half of VPP will set up a current through RL. This will drop the headroom on each half of the swing through R1 and R2:
By using Equation 5, a minimum required power-supply voltage may be computed:
The RL in the equation is the 2R from Figure 1. Using this and substituting the expression for the required VPP out of each amplifier gives:
A close look at the model reveals an additional design-optimization feature. Because it's ac-coupled, the xDSL line driver always delivers a symmetrical sourcing and sinking current into the load. Most often, if the amplifier under consideration provides enough information to extract both R1 and R2 separately, it will be found that they're unequal. At the peak currents, this means that an asymmetrical headroom is required for linear operation.
This can easily be accomplished by moving the output dc voltage for the driver to give a symmetric headroom at the peak currents. Using the peak-current equation for IP, the output dc-operating point must be set according to the following equation to keep an equal headroom at each peak for best linearity:
This basically involves taking the delta in the headroom reductions at the peak current and adding half of that to the supply midpoint. A bipolar-supply design would operate with the output shifted from ground by the amount given by the second part of the equation for common-mode output voltage VCM (see Equation 8). Shifting the output dc-operating point in this way will improve the second-harmonic distortion at the full-scale peaks.
A key, and sometimes overlooked, aspect to xDSL line-driver design is the power the driver amplifiers must dissipate internally to deliver the load power. The designer must recognize that the load power, while it does come from the power supplies, isn't the same thing as the power dissipated in the driver amplifiers. Even for equal load (or line) powers, there are significant differences in the driver power dissipation, depending on the details in the requirements. For this analysis, assume that the driver is in fact a dual-channel device sharing the same package. The internal power dissipation may be broken into two components:
- The quiescent power dissipation needed to operate the amplifiers
- The power dissipated in the output stage transistors to deliver the load power
The first of these is simply the quiescent current (IQ) times the power-supply voltage. The second is a little more interesting to derive. Figure 3 shows the output-stage circuit used to analyze power dissipation. Again, it assumes single-supply operation, but the same philosophy applies to bipolar supplies. The two sets of transistors are actually the output stages of two amplifiers. But because they're in the same package, they can be considered together for power-dissipation purposes. This is obviously an H-bridge structure with a purely ac output signal.
All xDSL signals are extremely complex in the time domain, not lending themselves well to a direct calculation of power using the time waveforms of voltage and current. Yet we do know the target average line power. The RB in Figure 3 is the total load between the two outputs of Figure 1. This is the sum of the two matching resistors in Figure 1 and the line impedance reflected through the transformer (RB = 4R in Figure 1).
With the matching resistors in place, the average power dissipated in RB is twice the desired line power (since impedance-matching resistors dissipate half the power in getting to the load). There's an easy way to calculate the power dissipated in Q1-Q4. First, compute the average current drawn from VCC to deliver this total load power. Then multiply that by VCC to get the total supply power delivered in Figure 3. Finally, subtract the power delivered to RB. This leaves the remaining power to be burned in Q1-Q4. Equation 9 computes IAVG from the power delivered to RB:
Using this average current, the total output-stage power dissipation is:
Substituting for VCC from Equation 7 and for IAVG from Equation 9 gives an output-stage power P0:
If we then take total driver power to be the sum of the quiescent power in each amplifier (2VCC*IQ) plus the P0 of Equation 11, we get Equation 12 (see the Equation Listing). Getting everything in Equation 12 in terms of the line power and impedance provides the total driver-power dissipation, Equation 13 (when the supply voltage is optimized to that given in Equation 8).
This analysis, using the minimum supply voltage, gives the lowest achievable internal driver power for a particular design. In practice, of course, the supply voltage will actually be higher than that computed by Equation 7. The turns ratio may be designed specifically to get Equation 7 to solve for the intended supply voltages.
The other assumption in using Equation 13 (see the Equation Listing, again) for a particular amplifier is that the amplifier's IQ doesn't change with supply voltage. This is commonly the case for most good designs, in which supply-independent biasing is used to maintain performance over a range of amplifier supply voltages.
Equation 13 will, in fact, show a shallow minimum versus turns ratio. As the turns ratio increases, the computed allowed minimum supply voltage decreases, dropping the quiescent power dissipation more than the output-stage power increases. As the turns ratio continues to increase, the allowed reduction in supply voltage stops decreasing (due to the high voltage drops in R1 and R2 as the required peak-output current increases), and the output-stage power continues to increase as given by Equation 10.
To this point, the discussion has been completely general, with no specific constraints on the amplifiers themselves. Before diving into the details of an example design, several important observations should be made:
- It's almost always advantageous to use current-feedback-type amplifiers in the line driver. As the turns ratio is modified, the required output voltages will change directly. Using a current-feedback-type amplifier, when coming from a specific codec's output with its own defined peak-output voltage, will allow the gain provided by the driver to be freely adjusted. And the adjustments have little impact on ac performance (changing the gain of the voltage-feedback op amp will directly impact its bandwidth and distortion).
As codecs move to 3-V CMOS, their smaller output-voltage swing will necessitate even higher gains in the driver. Current-feedback-type drivers will roll with these changes more gracefully. In general, the much higher slew rate of a current-feedback operational amp (for a given quiescent current) provides a comfortable performance margin when the design requires very low distortion levels at high powers.
- Although devices with both the driver and the receiver amplifiers on one chip are available, they must be approached cautiously for at least two reasons. In most cases, there are stringent isolation requirements between the receiver and the driver. Considerable care in the external circuitry is devoted to this issue. Putting them in the same package creates another level of possible crosstalk, particularly where high drive currents couple the two through the power supplies.
Secondly, the driver commonly operates at relatively high internal powers, often raising the die operating temperature well above ambient. Although the effect may be minor, it hardly seems desirable to operate the receiver at elevated temperatures and take an unnecessary hit in noise performance.
- There's been a tendency to use the same line driver at both ends of the line, because the analog front-end chip is often the same at both ends. But for highly asymmetric transmit power levels, like those in ADSL, employing the central-office driver as the customer premises' driver is probably overkill. The analysis tools developed here will allow an optimized design to be created for each end of the line. Also, in most cases, they will use different driver solutions where the required line power (or frequency) varies significantly.
The easiest way to see the effects of increasing the transformer's turns ratio is to use the equations derived above at several turns ratios. This was done for an example design of a full-power ADSL upstream driver. The table shows the result for the required amplifier output voltage, current, minimum supply voltage, quiescent power dissipation, output-stage power dissipation, and total power dissipation. Turns ratios of from one to four were used. The device used was the OPA2681, a very-wideband, dual, current-feedback op amp.
The analysis computes the supply voltage needed to support the required output voltage from each output. But it doesn't address whether the amplifier can deliver the needed current. One design approach is to look for the turns ratio that will require a supply voltage suitable to the amplifier selected (and the desired system power supplies), while requiring less than the maximum available output current for that amplifier.
In this design, a turns ratio of two will require a 7.5-V p-p output from each amplifier with a peak-output current of 150 mA and a minimum supply voltage of 11.44 V. With a single +12-V supply, this output current is within the capability of the OPA2681.
The table also shows that the required total supply voltage across the two output-driver op amps initially decreases rapidly with an increasing turns ratio. But as the impedance-matching resistors decrease to a level similar to that of the R1 and R2 resistors in series with the output-stage devices, the required supply voltage stops falling as the turns ratio increases. This again shows the diminishing utility to increasing the ratio.
Furthermore, the table reveals that the quiescent power dissipation initially decreases with supply voltage more than the output-stage power increases. This stops being the case after a turns ratio of about 1.8, because the increase in the output-stage power exceeds the decrease in quiescent power.
It's interesting, however, to observe the impact of increasing CF on power efficiency. The design point in the example delivers 20 mW to the line while drawing a total power from the supply of 420 mW + 40 mW = 460 mW. This is a 4.3% power efficiency. By keeping the same line-power targets and optimizing the turns ratio for minimum driver power in each case, the power efficiency would increase to about 8.4% if the crest factor decreases from 5.3 to 2.5 (Fig. 4).
A basic driver design was created using the information from the table for a 1:2 turns ratio. The maximum amplifier output must swing 7.5 V p-p into what appears to be a 25-Ω load while delivering 150-mA peak current (Fig. 5).
The example circuit includes some input and output components added only for test purposes. One is the 1:1 input transformer, which was added to supply the differential input expected by the driver. The center-tap on the input transformer secondary is set to the optimized +6.5-V bias point by a resistor divided off the +12-V supply. The 50 Ω across the secondary is for test purposes only, to get the required test-signal input impedance matching.
The design is set up for a differential gain of 7.5 from a maximum 2-V p-p differential input to the maximum required 15-V p-p differential output swing. Because the OPA2681 is a wideband, high-slew-rate, current-feedback design, ac performance holds up very well as the gain is increased to this 7.5 value. The output stage for this device (patents pending) also has been optimized to deliver high currents with minimal voltage headroom while retaining very low distortion on a low 6-mA/channel quiescent supply current.
The dc gain is set to 1 by the 1-µF blocking capacitor in series with the 100-Ω gain resistor. This is so the +6.5-V input bias voltage can be passed on to the output as an optimized center point for the output swing. With no input signal present, both outputs are sitting at +6.5 V with no current through the output transformer. At the amplifier outputs, two 12.5-Ω resistors (both labeled R in Figure 1) match into the 1:2 transformer, whose secondary emulates a 100-Ω load while still matching into a 50-Ω measurement system. In an actual application, the two 71-Ω resistors would not be used.
Driving a full 15-V p-p single-tone output, this circuit delivers over 60 MHz of bandwidth (Fig. 6). The circuit also has very low spurious levels at the ADSL upstream frequencies, which max out in the 138-kHz region. Two-tone, full-power (7.5 V p-p on each tone) intermodulation, spurious-free dynamic range is shown in Figure 7.
To support PC-based applications with single +5-V supplies, a different design point for the ADSL line driver is required. Given a 5-V supply to work with and a full upstream power of 13 dBm, the circuit would require peak currents and transformer turns ratios exceeding system design constraints. The G.Lite upstream power of 10 dBm with a 5.33 crest factor is, however, within reach of a single +5-V design.
Because every bit of voltage swing from the supply will be needed, a CMOS amplifier with rail-to-rail output swing appears to be the best design. Using the output-stage headroom (0.2 V) and series resistor values (R1 = R2 = 5.8 Ω for the DRV1101 high-current output differential driver) in the design spreadsheet gives a solution at a 1:3.2 turns ratio where a 6.7-VPP differential voltage is required with 170-mA peaks. The apparent load to the driver for this design is a very demanding 20 Ω. The patent-pending output stage design of the DRV1101 will deliver this power while meeting the distortion targets of G.Lite.
The 24-mA quiescent current on a 5-V supply, along with the internal power dissipated to deliver the load power, as discussed previously, gives this design a 260-mW internal power dissipation. The receiver-channel amplifier requirement can again be met by the low-noise OPA2680, this time operating on one +5-V supply. Since the voltage on each output of the OPA2680 can swing 3-V p-p (with greater than 150-MHz bandwidth), even the most demanding AFE input requirements can be met.
- Harris Application Note AN9718, "Analog Amplifier Linearity Characterization Via Probability-Weighted Multitone Power Ratio Testing (HI5905)."