Because of its low-power and low-noise characteristics, the low-voltage differential-signaling (LVDS) standard technology is an important candidate for the physical layer in high-speed data-serializing schemes. It provides more than twice the noise margin of reduced-swing single-ended technologies such as BTL and GTL+ without a great speed penalty. Originally intended for parallel interconnects from a few inches to tens of meters, LVDS' characteristics were initially valued primarily in graphics applications. However, recent trends toward serializing high-speed data in areas ranging from server backplanes to clamshell cell-phone hinges are leading to a broader application range.
There is no maximum data rate for LVDS. Current standard parts operate from dc to many gigabits/s. Chips for point-to-point and multidrop applications have existed for a while, but lately there's a growing list of products for multipoint (bus) applications. Beyond backplane and cable applications, the availability of standard parts is important because it often proves necessary to buffer LVDS I/Os in ASICs and FPGAs.
The Standard
The LVDS standard is designated ANSI/TIA/EIA-644-A-2001, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits. It defines only driver output characteristics and receiver input characteristics, although it provides guidelines for bus configuration, cables, and termination. Protocol, connectors, and bus structures depend on the application and must be specified by the referencing standard.
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