Some new wireless and communications applications like basestations require 16-bit resolution as well as high sampling speed. Devices with high sampling rates are readily available, but some analog-to-digital converters (ADCs) require transferring all that data over a 16-bit data bus with a minimum of 16 lines, and, in some cases, 32 lines. That not only takes up lots of board, it also can introduce noise and crosstalk.
Linear Technologies’ LTC2274 serial-output ADC solves this problem (see the figure). It offers a sampling rate of 105 Msamples/s, but other versions can be had with a rate of 80 or 65 Msamples/s. The two-line serial interface output uses low-voltage differential signaling (LVDS). The serial output, which typically will drive a larger IC such as an ASIC or FPGA, is serialized in accordance with the JEDEC JESD204 specification.
The LTC2274 uses 8B/10B coding, and its data rate can be as high as 2.1 Gbits/s. The output is compatible with some popular Altera, Lattice, and Xilinx FPGA chips. Also, the device offers a 78.2-dBFS noise floor, a 100-dB spurious-free dynamic range (SFDR), and a 700-MHz input bandwidth. The supply voltage is 3.3 V, and power consumption is 1200 mW. An internal dither feature is available to improve SFDR with very low input signal levels.
Samples and demo boards are available now with full production available after August. The LTC2274 costs $68 in 1000-unit quantities.
Linear Technology Corp.
