Using Delta-Sigma Can Be As Easy As ADC (Part 5)

April 23, 2009
Part 5 of a tutorial on Delta-Sigma data converters addresses higher-order Delta-Sigma modulators

My last column showed how a single-stage delta-sigma modulator (DSM) produces an output that is a sum of the low pass-filtered input signal and the high pass-filtered quantization noise (see “Part 4,” Jan. 29, p. 18; ED Online ). The primary difference between a filter and a DSM is that a filter feeds back its output while the DSM feeds back its quantized output. If this is all you take away from this series of columns, it is enough to justify my effort.

The high pass filtering of the quantization noise pushes it to a higher frequency, allowing easier removal with a decimation filter. Reducing the filter bandwidth by a factor of four (two octaves) decreases the noise by a factor of eight, or 18 dB (Equation 1):

The noise reduction is 9 dB per octave. And as with filters, if you need more performance, you just increase the number of sections. If a single-pole filter isn’t adequate, make it two, three, or more poles. The same goes for DSMs (Fig. 1).

If the quantization circuitry were removed, it would be an ordinary two-pole low pass filter. When we add the quantization hardware, the output becomes the sum of the low passed-filtered input signal and the high passed-filtered quantization noise. Setting the RC time constant to match that of the sample clock (RC = 1/fS) results in Equation 2, relating the output voltage to the input signal and quantization error:

As with the first-order modulator, the output is a sum of the low pass-filtered input signal and the high pass-filtered quantization noise. But with the second-order modulators, the rolloff is enhanced. The relative amplitude of both the signal and the quantization noise can be plotted as a function of frequency (Fig. 2).

Along with the quantization plot, the single-order DSM quantization is added to show the difference in the noise spreading. The plot shows that the quantization noise has been pushed (shaped) further toward the higher end of the spectrum. At a fairly low frequency, its relative response is roughly parabolic. Equation 3 shows the response:

sample rate (f0). The amount of noise below this value is even smaller than with a single-order DSM. To calculate the total quantization noise, each bit of the noise left in this band must be added (Equation 4):

A reduction of two octaves reduces the in-band quantization noise by 30 dB. With the proper filter, it is possible to achieve 15 dB/octave. For a second-order modulator with a 1-Msample/s clock and the proper decimator, it is possible to get 16-bit resolution at 7.8 ksamples/s. This is better than the 488 samples/s for the single-order DSM obtained in Part 4 of this series of columns.

EVEN HIGHER-ORDER DSMs Just like filters, higher-order modulators can be built with the addition of integrators and quantization feedback. An “L” order modulator will have “L” integrators and “L” feedback loops. (L is for loop.) It also will have the following band noise (Equation 5):

The noise reduction will be 21 dB/octave for a third-order modulator, 27 dB/octave for a fourth-order module, and so on. Given a 1-Msample clock, a third-order modulator with the correct decimator will result in 16-bit resolution at 25 ksamples/s. A fourth-order modulator should have the same resolution at 50 ksamples/s.

Developing practical higher-order modulators isn’t an easy task. As with filters, practical designs come with experience. My goal in writing this series has been to show how delta-sigma modulators operate. This way, when you see a data sheet for a part with a sixth-order DSM, you will understand that its resolution enhancement is 39 dB/octave and how it is possible to get so much resolution with such a relatively small system clock. For real examples, I built first-, second-, and thirdorder delta-sigma modulators, each with a 250-ksample/s clock. They were constructed using a Cypress CY8C27443 programmable system on a chip. The input was a 100-Hz sinusoid, and the digital output was fed to a Hewlett-Packard 3585A spectrum analyzer. Figure 3 shows the results for the three difference modulators. It is apparent that the noise gets lower as the modulation order increases.

SUMMARY Delta-sigma modulation appears complicated, but it can be made easier to understand viewed from a historical perspective. By starting with single-slope converters and moving to dual-slope, single- stage DSMs, and finally to multi-order DSMs, the motivations for each increment becomes apparent in how each improved performance and reduced cost. No grand plan. No intrinsic beauty. Just simple engineering practices applied over time.

For those interested in building their own DSMs, I have projects for single-, dual-, and triple-order modulators. These projects work with the chip earlier discussed. You can get a copy by e-mailing me.


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