Devices Combine Two NPN Transistors

Oct. 1, 1999
The UPA Series Twin Transistor devices now come in smaller, lower profile TC 6-pin packages with a height of 0.55 mm and a smaller footprint than SOT-363 for applications such as cell phones, PCS handsets, PCMCIA cards, miniature VCOs, pagers, keyless

The UPA Series Twin Transistor devices now come in smaller, lower profile TC 6-pin packages with a height of 0.55 mm and a smaller footprint than SOT-363 for applications such as cell phones, PCS handsets, PCMCIA cards, miniature VCOs, pagers, keyless entry transmitters, and other portable wireless products. This TC package has a flat lead design for reduced parasitic lead inductance and better electrical performance than devices with gull-wing style packages. The UPA Twin Transistors come two ways: with paired adjacent die from the same wafer for closely matched electrical characteristics providing less tuning for applications such as two-stage LNAs, and mixed die to give designers flexibility to configure combinations for two-stage amplification.

Company: CALIFORNIA EASTERN LABORATORIES

Product URL: Click here for more information

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