Three Industry Leaders Track Analog Chip Trends

Jan. 7, 2010
Linear Technology's Bob Dobkin, Mentor Graphics' Robert Hum, and the Gartner Group's Steve Ohr assess the future of analog chips from different perspectives: process technologies,design and verification/validation tools, and market demand.

It used to be easy to pin down analog and mixed-signal electronics. The basic building blocks included amplifiers and data converters. Chip companies specialized in continually improving those blocks. And, very special engineers could put them together into useful designs.

Today, new chips tend to combine multiple functions with an eye toward specific applications, fabless startups regularly challenge mainline chip companies, and analog-circuit wizards like Bob Pease are growing scarce.

To get a line on where analog is heading, we spoke with three gurus: Linear Technology’s VP and chief technical officer, Robert Dobkin; Robert Hum, the VP and general manager of Mentor Graphics’ deep-submicron division; and analog industry analyst Stephen Ohr of Gartner Inc.


Q: What do you think about building analog and mixed-signal chips on a foundry’s state-of-the-art CMOS process tech-nology versus an analog-specialty company’s dedicated in-house technologies?

A: It depends on what you’re looking for. Almost all logic is made from CMOS because of its improved density and its ability to handle the ones and zeros at low power. With analog, that is not the case! Bipolar and CMOS are different tools, and bipolar transistors are still the best transistors in many types of analog circuits.

RF ICs, precision amplifiers, references, and low-noise signal processing all require bipolar transistors for highest performance. Many of these bipolar transistors and various CMOS types are unique to the analog IC manufacturers and not readily available at foundries. This yields analog ICs that are unique to the manufacturers and to their internal semiconductor fabs.

Also, bipolar transistors are not subject to the same lithographic shrinking that MOS devices enjoy, so the density of bipolar transistor circuits remains relatively constant with time. Some bipolar ICs introduced 25 years ago have the same chip size today and cannot be reduced.

Still, the continuing push for smaller line widths in digital ICs has had its effect on analog as well. These processes continually get faster and enhance the speed of analog ICs made on those processes. Analog-to-digital (A/D) converters are a good example where smaller line widths have led to faster A/D converters. Circuit advances improve the resolution as well as the speed, and new devices convert at 200 Mbits/s with 16 bits of resolution. There’s no reason to think that they will not continue to accelerate in speed and precision as techniques are developed to go faster and more accurately.

These smaller line widths make practical some digital functions that were previously impractical in analog ICs. Pow-er-supply controllers with digital readback of voltage, current, and status are achieved on the same chip as the power functions. A side benefit to the smaller line widths is the inclusion of DMOS transistors on the small-feature digital process. These DMOS devices can handle high voltage as well as high current and allow the complete integration of power converters, switching regulators with both power and control on the same device.

Q: How do you increase performance when you’re using mature processes?

A: Analog advances are usually the result of new circuit concepts that are developed in-house. These new circuits are often closely mated to the process, giving a synergistic result. Very few of these types of circuits cross manufacturer boundaries and rarely end up sourced by multiple companies in multiple products. This is unlike digital advances in process technology, which tend to be proliferated across the industry.

Accumulated knowledge about making complex functions in different processes continues to advance. This knowledge allows still higher-functionality mixed-signal ICs to be generated each year.

Circuit advances in bipolar technology with some process enhancements yield incrementally better references, amplifiers, and RF ICs. These enhancements are due to refinement in the circuitry and optimization rather then any type of breakthrough due to process. The competitive landscape for analog ICs keeps all manufacturers on their toes in trying to improve their products.

However, it should be noted that since analog IC performance is based on real-world parameters, the ICs can end up at theoretical limitations of performance. Once the theoretical limitation is approached, further improvements are just not possible. That’s why some of today’s bestselling and most widely used ICs were designed over 20 years ago and haven’t changed in the interim.

Q: Will analog circuits follow the price curve that digital circuits follow?

A: No! No! Buyers always want analog pricing to follow the same path as digital. That can never be the case! Analog IC die sizes and costs are dictated by the voltages and currents they manipulate. The cost is based on real-world parameters that are inherent to the IC. By the time digital ICs are four years old, they are obsolete and are being replaced by denser, smaller chips. After four years, the analog IC has only just been optimized and all production-cost reductions have been realized. Some 25-year-old analog ICs are still in high-volume production, and expecting 25 years of continuing price reductions is unreasonable.

Q: What’s the bottom line?

A: The changes in digital processing are enabling newer, higher-performance analog ICs where speed or the mixed-signal complexity has previously been a limitation. Circuit developments along with the process get back some of the precision lost by a move to a process with less precise transistor characteristics.

Bipolar and CMOS circuitry will remain steady in growth as its performance advantages continue to be refined. New breakthrough technologies in analog are few and usually only noticed after they’ve been in the marketplace for several years where their recognition comes from the number of circuits implementing these technologies.


Q: What is your current impression of the relationship between designers, fabs and foundries, and EDA companies?

A: Analog designers face daunting challenges below the 65-nm technology node. What once were annoying third-order layout-related effects are becoming primary parasitic circuit elements. These elements can cause a design to deviate from its intended operation so it no longer meets specifications or yield targets. Current design methods that are highly tuned to pre-65-nm nodes are forcing iterations through the fab to identify and correct issues causing these aberrations, leading to longer and more expensive design cycles.

For example, at 22 nm, it is even becoming important to understand how OPC (optical process correction) impacts basic transistor behavior and yield for certain highly dense circuits such as embedded SRAMs and DRAMs (see We believe that it will become essential for EDA tools to link electrical and physical design disciplines even more tightly together to deliver a successful, high-yielding SoC (system-on-a-chip) in the future.

Q: What about mixed-signal design?

A: The number of designs now incorporating analog blocks into predominantly digital circuits has increased dramatically, leading to serious verification issues due to the mixed-signal nature of these designs. The complexity of verifying digital circuits has increased tremendously in the last five years. We have seen VHDL and Verilog be supplanted by SystemVerilog and Open Verification Methodology (OVM) in reaction to this increase in verification complexity and decrease in efficacy of existing verification methodologies.

Many new concepts such as assertion-based verification (, cover-age-driven verification (, directed random patterns (, and more have been introduced into the tool base.

Now, with increasing analog content, our approach to the verification of mixed-signal circuits has to evolve rapidly to meet the new challenges. Concern over noise injection between analog and digital domains, the impact of power distribution and control, interfaces between digital and analog blocks, circuit sensitivity to local heating, proximity and strain related issues, and more requires new methods and tools so designers can continue to innovate and produce high-quality, complex SoCs.

Q: You deal with big-D, little-a companies and with big-A, little-d companies. The former are usually happy with the foundry’s generic mixed-signal blocks, while the latter tend to roll their own while collaborating with their foundry partners to squeeze maximum performance out of the process technology. How does an EDA company such as Mentor Graphics deal with their divergent needs? How do you deal with verifying/validating ac performance?

A: Classifying customers as either big-A, little-D or vice versa is too broad. We have customers known for being digital who develop substantial in-house analog blocks. We also have analog customers with their own fabs who integrate significant amounts of digital blocks as well as analog customers targeting sub-65-nm nodes of the major worldwide foundries.

We think it is more useful to view both analog and digital designers as part of a larger IC design ecosystem. Our cus-tomers fill different roles within the ecosystem. With continually shrinking geometries, increasing integration, and tightening resource and timeline restrictions, few companies have the luxury of considering the analog and digital design communities separately.

Although every design has its core value-add proposition—high-performance custom analog, large integrated mixed-signal SoCs, or high density/volume, to name just a few examples—each type of design is interdependent with the others, relying on a variety of external deliverables such as analog hard-macro IP, standard digital IP, and complex verification IP. Each of these customers faces the challenges previously mentioned.

Being able to efficiently capture and represent not only the design data but also the design sensitivities and constraints is necessary for producing high-yielding products with short development cycles. Each of these play a vital part in the design, verification, and validation of today’s complex analog and mixed-signal designs. Also, it is clear that the increasing impact of second- and third-order effects at the nanometer-scale process requires a highly integrated design environment with tightly linked EDA solutions.

Mentor Graphics supplies solutions that cover all areas of analog and mixed-signal product development from ana-log/mixed-signal design, layout, and verification with ICStation, Eldo, and Calibre to circuit and system verification with Questa ADMS. In addition to addressing today’s challenges, Mentor Graphics is planning to address the new parametric yield challenges present at sub-45-nm nodes by developing tools and methodologies that will completely change the current analog/mixed-signal design and verification paradigm.

Q: When does SoC have to turn into multi-die? With noise, what’s the smallest reasonable geometry for doing a PLL?

A: With regards to multi-die versus SoC, this tradeoff decision should not be made from the point of view of guard-banding the design against unpredictable implementation effects. The correct way to decide is by using methods and tools to capture and accurately predict these effects.

The data from these models and predictions should feed advanced analysis tools that allow for a well informed deci-sion. Guardbanding is no longer a viable solution. Again, Mentor Graphics has products today that are beginning to provide this capability, and we have plans for the future to completely change the analog/mixed-signal design and verification paradigm.

Finally, whenever you hear someone say “You can’t make it smaller,” just wait five or so years. Many smart engineers have been proven wrong when it comes to guessing at the limitations of semiconductor process and design limitations.


Q: Where are we headed?

A: It will surprise few to recognize that the revenue growth curve for standard analog ICs generally tracks the curve for semiconductors as a whole. Some years it grows a little faster than the rest of the industry. Some years it grows a little slower. But, over time, the envelopes are pretty much the same (Fig. 1).

Q: What’s hottest?

A: Among standard analog ICs, power-management devices, which Gartner forecasts as “voltage regulators,” remain the largest and fastest-growing segment. One reason is that power requirements are becoming more sophisticated with the proliferation of features and functions in electronic equipment.

A modern smart phone, for example, will use applications processors and baseband processors, five separate radio transceivers, many with their own specialized power amplifiers (PAs), each with their own voltage regulators. The voltage regulator count goes up with the proliferation of features like wireless Internet browsing, high-resolution cameras, touchscreens, FM radio, mobile TV, GPS, and location based-services.

While these regulators are increasingly integrated onto single-chip custom power-management ICs (PMICs), there are easily 22 to 26 voltage regulators per phone. (The PMICs, be aware, are counted as custom application-specific standard parts, ASSPs, and not with standard voltage regulators. The PMICs accounted for roughly $2.2 billion in revenues in 2009.)

The other reason voltage regulator revenues grow so rapidly is that the move to lower-voltage CMOS does not dry up the need for separate 12-V or 5-V parts, but in fact adds to it. Thus, the revenues for voltage regulators grow more rapidly than other standard analog ICs (Fig. 2).

Q: Can you break that down?

A: The analog voltage regulator segment, which was roughly worth $6.9 billion in revenues in 2009 (down from $8.5 billion in 2008, due to the recession), is actually experiencing some upheaval. With several variations, the market is split between linear regulators and switch-mode devices.

The linear regulators depend on a bipolar series-pass transistor, with an error amp in the feedback loop driving its base. The parts are very easy to use, available from a wide variety of sources, and consequently very cheap. But because the series-pass element is cooking away all the time, they are not particularly efficient.

The switch-mode regulators, in contrast, depend on pulse-width modulators to pump dc pulses across an inductor. They are not particularly easy to use, not particularly cheap, but they are quite a bit more energy-efficient (particularly with high current loads). The upheaval we’re seeing is a consequence of the need to improve energy-transfer efficiency in all electronic circuits.

Non-isolated dc-dc converters are expected to show good growth in those markets and applications that put a premium on energy transfer efficiency (Fig. 3). This has typically been large computer servers, communications switching stations, and enterprise-level routers where the higher cost of switch-mode devices can be amortized against the electricity savings in cooling and air conditioning.

An 80% efficient voltage regulator, remember, will still convert 20% of all the electricity you give it into heat. Thus, an 85% efficient regulator will dissipate less heat than an 80% device. A 90% regulator will dissipate less heat than an 85% device, and so forth.

But certain types of consumer devices are expected to increase their consumption switch-mode parts in an effort to improve their energy-efficiency ratings. In addition to a proliferation of dc-dc converters used as LED array drivers in LCD TV backlights, we’ll see a replacement of high-current linear regulators with dc-dc switch-mode parts in set-top boxes and in plug-in battery chargers. Non-isolated dc-dc converters will consequently show the highest revenue growth of all types of voltage regulator types. Revenues for linear regulator parts will be almost flat in comparison.

Q: So what can we expect?

A: There are three trends to watch for. First, look for dc-dc (and ac-dc) converters to be deployed as LED string drivers in halogen bulb replacements. Second, look for dc-dc converters to be increasingly deployed as motor drivers in household appliances like refrigerators, washing machines, and dishwashers.

And third, look for digital interfaces on new-generation dc-dc converters, especially BCD (bipolar CMOS DMOS) devices, using a 0.18-µm CMOS substrate to support bipolar transistors and DMOS power devices on the same chip. This will be the likely platform for digital power management and control.


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