Take Time For A Clock-Chip Update

April 15, 2010
A refresher and update on designing clock chips into communications and industrial control applications

Phase noise

Four common ways to terminate

Modulation profile

MEMS resonators

The beating heart of mixed-signal processing is delimited by the clock devices that slice the analog world into digital events. Like our own hearts, we don’t pay much attention to them unless something goes wrong. When it does, it pays to know something about the various ways these silicon tickers can act up.


In choosing clock chips for high-performance data converters, the most critical datasheet characteristic is jitter, which translates to phase noise in the frequency domain (Fig. 1). You can look at the jitter as uncertainty in the placement of the data conversion. But from an analytical standpoint, it may be useful to look at that phase noise as a limitation on signal-to-noise ratio (SNR). Really high-performance, high-speed converters require clocks with RMS jitter below 200 fs.

For converter applications, broadband RMS additive jitter is a good specification to compare. For networking applications, specific offset bandwidths, such as 12 kHz to 20 MHz or 5 to 80 MHz, are typically specified. Either way, be sure to check the conditions for measurement. A faster slew rate, for example, will result in better SNR in data-converter applications. Additionally, measuring over a restricted band of offsets reduces jitter magnitude.

To achieve the highest SNR, you should choose the lowest possible jitter under your conditions. If the number of outputs isn’t high enough, add fan-out clock buffers of less than 100 fs to avoid inserting too much additive jitter into the clock chain.


“Tidy is as tidy does,” they say. If you want to avoid clock-related problems, you have to keep the clock signals on the printed-circuit board (PCB) traces where they belong and off of adjacent traces and power-supply lines. That means good layout with proper terminations bypassing where needed, as well as edge control.

For clock distribution, the most common methods for terminating transmission lines are series, parallel, Thevenin, and ac terminations (Fig. 2). Series termination occurs at the driver end of the line. The other methods deal with reflections at the receiver end.

To make a series termination, connect the resistor in series with the driver output pin and the trace. Choose the resistor value so it and the output impedance of the driver add up to the characteristic impedance (Z0) of the transmission line.

Series termination and the driver output impedance add up to be less than the line characteristic impedance, as it is for most transistor-transistor level (TTL) or low-voltage CMOS (LVCMOS) drivers. Series termination does not waste power by shunting some current to ground, which is a good thing. But it does have a negative impact on the rise/fall time of the clock transition, so there is some increase in jitter susceptibility.

In parallel termination, the clock input of the chip that is being driven is tied to ground with a resistor that has a value of x times Z0. The line is properly terminated, but current through the resistor represents a certain amount of power loss. That leads to the Thévenin termination, in which there are two resistors at the input to the driven device, one to VCC and one to ground. There is less power loss, though at the cost of adding an extra part.

That leaves ac termination, in which a capacitor blocks dc power flow, resulting in low losses but with the penalty of an increase in propagation delay. In ac termination, resistor values are generally sized larger than Z0 – 75 Ω, rather than 50 Ω, which creates a small mismatch yet offers the advantage of reducing leakage at the input stage of the receiver. There are tradeoffs to consider in choosing a capacitor. It’s generally sized larger than 50 pF. That’s considered sufficient to sink the ac current. However, larger values up to 120 pF allow faster clock transitions.


Noise doesn’t just affect the circuit being clocked. It can affect the world at large, or at least other electronic devices within a few meters of your design. Curiously, for dealing with radiated electromagnetic interference (EMI), we use spread-spectrum clocking (SSC), which is all about deliberately adding jitter to a clock.

With SSC, you pseudo-randomly dither the clock frequency to spread its energy spectrum over a wide frequency band, rather than have its energy concentrated at the clock fundamental frequency and its odd harmonics. This reduces the peak energy, which often allows the design to meet the requirements of the application. Those requirements may include the FCC part 15 (Title 47 CFR Part 15) regulation that applies to “unintentional radiators.” Essentially, it provides a profile of allowable field strength across the RF spectrum.

Not everyone is happy with the engineering decisions that were made in establishing the Part 15 limits because they don’t specify a maximum level of emitted energy. With a spread-spectrum radiator, the measuring equipment in effect averages the energy across a period of time while the interference from class A or B (B has the more stringent spec) dithers with the switching frequency.

As one Electronic Design reader recently complained, “We’ve traded birdies at specific frequencies for a general hiss across the entire band.” As a practical matter, electronic equipment that is sensitive to a narrow band of frequencies sees less interference while equipment with broadband sensitivity to EMI experiences more interference.

Nevertheless, Part 15 is what we have, and spread-spectrum clocking is what allows clocks and switching supplies to meet Part 15 requirements. Given that, design parameters for spread spectrum clocking include modulation index (d), modulation frequency (fm), modulation profile, and spread type.

Modulation index is the frequency variation (spread) of the clock signal, expressed as a relative percentage of the nominal clock frequency, fc. For example, ±1% spread means that a 100-MHz clock is jittering pseudo randomly between 99 and 101 MHz. The greater the value d, the more reduction in EMI, but the greater the jitter in the clock signal.

Modulation frequency refers to the rate at which the clock frequency varies between fc and (1-d)fc. Usually, fm is a little greater than 30 kHz, which keeps it out of the audio band but well below the system clock.

The modulation profile (Fig. 3) describes how the clock frequency is modulated. In the time domain, the profile that provides the most evenly distributed spectrum is patented by Lexmark International. It resembles the shape of a Moorish arch or a “Hershey’s Kiss.” More often, one sees a triangular “Shark Fin” sweep profile, which results in some rippling at the ends of the frequency spectrum.

The spread type we’ve been talking about, where there is variation on both sides of the nominal clock frequency, is called “center spread.” Alternatively “down spread” varies between fc and a lower frequency determined by d. Obviously, the only practical difference is in the nomenclature. But in comparing datasheets, it helps to be clear on the type of spread being specified.


With respect to radiated interference, shielding offers an alternative to the SSC approach. There are other approaches for conducted interference, which is more prevalent at lower clock frequencies (below about 30 MHz).

Shielding uses conductive material to wrap up the EMI completely to ground. This keeps electromagnetic energy inside the system. It also makes it harder for an external signal to create EMI in the system. Shielding is useful for both conducted EMI and radiated EMI. However, it doesn’t work well in some cases.

At lower frequencies, radiation is almost exclusively via I/O traces. How far radiated interference gets depends on the radiating conductor’s height above the ground or power plane and the length of the conductor in relation to the wavelength of the signal component (fundamental, harmonic, or transient such as overshoot, undershoot, or ringing). RF noise from clock and signal lines also gets onto the power planes and is coupled to the line drivers via the VCC and ground.

The RF is then coupled to the trace through the driver as common-mode noise. Because the noise is common mode, shielding has very little effect, even with differential pairs. In that case, the RF energy is capacitively coupled from the signal pair to the shield, and the shield itself does the radiating.

One cure for this is to use an RF choke to reduce the common-mode signal. Good decoupling and layout can reduce EMI more effectively than shielding. Decoupling capacitors on each active device (connected across the power supply as close to the device as possible) provide a low ac impedance path to ground.

The recommended approach for maximizing bypass bandwidth is to use multiple capacitors with capacitance values separated by two decades—for example, 0.1 µF and 1 nF. Best practices recommended in some Texas Instruments application notes include placing the lowest-valued capacitor as close as possible to the device to minimize the trace’s inductive influence. This is especially important for small capacitor values because the trace’s inductive influence is considerable at higher frequencies.

In terms of layout, other TI best practices recommend keeping the ac return path short. Multilayer boards make it reasonably simple to distribute power and ground planes beneath clock and signal traces. Actually, running clock signals between a pair of grounds is particularly effective, when economics permit.


Heuristically, it’s easy to see that clock jitter—uncertainty in precisely when the transition that triggers a sampling event takes place—is undesirable because it in effect “blurs” the measurement. In more analytical terms, clock jitter in the time domain can be equated to phase noise in the frequency domain. That phase noise spreads some of the clock’s power away from its fundamental.

Why is that important? In general, the process of sampling an analog signal for the purpose of digitization is equivalent to mixing or multiplication in the time domain or convolution in the frequency domain. In other words, the spectrum of the sample clock is convolved with the spectrum of the input signal.

In that case, if you consider jitter to be wideband noise on the clock, that wideband noise is also present in the sampled spectrum. Its spectrum is periodic and repeated around the sample rate. It also raises the noise floor.

That analysis gets one out of heuristics and into mathematics. It is then possible to analyze the effect of phase noise on SNR. A clock time delay is equivalent to a phase delay at a given frequency. In terms of noise power, this implies that phase noise in rms radians, σθ2 equals ω2CLK × σt2, where σθ is the phase jitter in rms seconds and ωCLK is the clock frequency in radians/s. In other words, for any value of jitter error, a higher-frequency signal will have a greater phase error. Phase noise relates to the clock SNR by:

SNRCLK(dB) = –10 log σθ2

When the bandwidth of the clock jitter falls into a single Nyquist zone (and making some other simplifying assumptions), the SNR of a signal, f0, sampled with a jittery clock, is:

SNRsig (dB) = 1/(4π2 × σt2 × f0)

Getting a bit more complicated, in multi-carrier narrowband systems, the SNR—this time expressed in dBc (i.e., referenced to one of the carriers)—would have the same form. The sum of all the frequency terms, though, would replace the f0 term in the denominator. This raises the quantization and thermal noise floor, so in these applications, jitter may not contribute as greatly to the overall SNR as do quantization and thermal noise.

But in wide-band systems, assuming the energy in the data signal averages out to zero and that it exhibits a flat spectrum uniformly distributed between two frequencies, fL and fH, it can be shown that:

SNRsig = (1/σt2) × 3(/fH2 + fHfL + fL2)

In a third case, that of under-sampled systems in which the signal frequency occupies one of the higher Nyquist bands, it is necessary to provide clocks with much better phase jitter than in the baseband systems discussed above. This is because, if the jitter is large enough, and the sampled signal falls close to a Nyquist edge, the noise caused by jitter can alias back in-band. In these applications, SNR limitations due to jitter can be determined by:

SNR(dB) = –20 log(2πfanalog × trmsjitter)

where fAnalog is the input frequency and t is the jitter.

Given a frequency of operation and an SNR requirement, the clock jitter requirement can be determined using:

tJitter = (10–SNR/20)/2πfanalog

In other words, If jitter were the only limitation to converter performance, to sample an IF signal of 70 MHz while maintaining a 75-dB SNR, you would have to limit maximum clock jitter to 400 fs.

Interestingly, the level of jitter or phase noise that can be tolerated in high-speed data-converter applications is more stringent than it is for very high-speed communication. For instance, although SONET/SDH specs permit clock jitter on the order of a few ps, for a data converter operating at 100 MHz, with analog input frequencies of 70 to 200 MHz, jitter must be less than 1 ps.


For a considerable time, the universe of clock-generation devices was dominated by quartz-crystal and surface acoustical wave (SAW) devices surrounded by a variety of buffer, fanout, and delay-compensation chips. Recently, this has been changing. New products from companies such as SiTime, SpectraLinear, and Zarlink are representative.

SiTime offers microelectromechanical-systems (MEMS) oscillators, rather than clock generators. The company points out that an oscillator integrates the resonator and the oscillation circuitry inside a small package and outputs a single clock signal, while a clock generator is a much larger device that requires an external reference resonator and usually incorporates one or more multiple phase-locked loops (PLLs) to generate the clock outputs.

Now, SiTime says, MEMS are displacing quartz resonators in timing applications. These MEMS resonators (Fig. 4) are a fraction of a millimeter across and vibrate at megahertz frequencies. They’re built on mainstream CMOS process technologies. Under an electron microscope, they reveal themselves as ring-like structures, and according to SiTime, their vibration modes are similar to the modes of the lips of tiny bells.

While the MEMS structures have been evolving, so have the associated electronics, going beyond simple amplifiers that buffer the output of the old quartz crystals. The main difference is programmability, including the ability to program output frequency across a wide spectrum.

SiTime’s MEMS oscillators are unique in the way they achieve this. These oscillators use the same MEMS resonators for every output frequency. The frequency output of the oscillator is determined not by the physical dimensions of the resonator, as in crystal-based devices, but by programmably multiplying-up the fundamental frequency of the MEMS device.

This lets SiTime provide flexibility without the need for a large inventory of custom parts. Engineering samples can be made immediately using portable programmers or at the factory in one day. Naturally, it also makes manufacturing and material flow very efficient, leading to shorter lead times and low pricing.

In this regard, SiTime points out a difference between its oscillators and earlier programmable quartz oscillators that used ring oscillator PLLs that produced jittery outputs. The company’s Sigma-Delta Fractional-N LC PLL is different. SiTime says it reduces clock jitter to levels comparable with or better than fixed-frequency oscillators.

Interestingly, because the MEMS resonators are thinner than any packaged quartz crystal, they allow SiTime to package particularly thin oscillators—down to 0.25 mm. Standard footprints are 2.5 by 2.0, 3.2 by 2.5, 5.0 by 3.2, and 7.0 by 5.0 mm. But the very low height profile compared to crystal oscillators makes them particularly appealing in mobile products.

Product families are differentiated by application area. In the high-performance family, with output frequencies up to 800 MHz, integrated phase jitter is less than 1 ps and rms jitter is less than 3 ps. Low-power oscillators, programmable to any frequency between 1 and 110 MHz, draw under 3.5 mA from 1.8 to 3.3 V and start up in 3 ms. Another line offers programmable spread-spectrum dithering, and a line of multi-output oscillators in single packages is intended for systems that require multiple clock frequencies.

SpectraLinear’s programmable EProClock spread-spectrum clock generators are partly a product-cost sell. The company says they provide the same performance as high-performance crystal oscillators, SAW oscillators, or voltage-controlled oscillators, but cost significantly less.

Yet even more, the story is about faster development time and short ordering leadtime. SpectraLinear says they provide considerable on-the bench flexibility with an extensive library of multiplexers and programmable elements. Available within hours or days of product definition, the company says, each product has more than 2000 control points.

The parts promise to cut out delays associated with ordering customized parts by making it possible to optimize any device for its intended application by programming operating speed, spectral phase noise, timing jitter, power, heat, and radiated emissions. This includes programming output frequencies from 3 to 200 MHz using either crystal or clock input. By programming drive levels, designs can accommodate seven different rise and fall times.

For spread-spectrum, it is possible to individually program frequency (25 to 120 kHz), spread (0.25% to 5.0%, center or down), and profile, (Lexmark or Triangular). These can be programmed in-circuit, which helps minimize test time while ensuring that products meet Part 15 standards. Similarly, designers can vary clock output drive strength and adjust rise and fall times on the bench to perform noise sensitivity analysis.

Also, there are seven independent programmable output drive-strength levels for each output. Jitter performance can be traded off for power dissipation. Single-PLL generators may have up to four clock outputs. Four-PLL generators may have up to 12. On-chip crystal-load capacitors eliminate the need for external crystal load capacitors.

Zarlink’s novel is to approach is to shrink the solution size by squeezing everything needed for clock generation onto a single chip. The company notes that traditionally, a large number of clock oscillators, crystals, and fixed-frequency clock generator and multiplier ICs have been required to satisfy the diverse clocking requirements of CPU, memory, DSPs, framers, physical layers, and other components.

Yet Zarlink notes that new single-chip silicon clock generation products can effectively manage and control dataflow across multiple components for a range of applications. Beyond board space advantages, the company says, these single-chip solutions reduce power consumption, ease system validation, simplify frequency margining, and help improve overall reliability. Most importantly, Zarlink claims, their unique architecture supports any rate to any rate frequency translation, where traditional M/N and fractional-N multiplication have frequency and performance limitations.

Zarlink’s ClockCenter platform for high-speed optical transport network (OTN) and communications equipment comprise multichannel synchronous clock translators and free-run clock generators. They provide “any-rate to any-rate frequency translation,” according to the company. Specifically, ClockCenter synchronous products accept and generate any frequency (1 kHz to 720 MHz). ClockCenter free-run products were developed to allow designers to replace multiple oscillators, logic converters, and fan outs to time processors, memory chips, physical-layer (PHY) chips, and other components with an integrated single-chip device.

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