Lower-Power Delta-Sigma ADC Design

March 24, 2011
Consideration in chip design and process technology selection related to the performance of Delta-Sigma analog-to-digital converters.

A typical feed-forward modulator for ?S ADCs shows how this topology can limit or eliminate the input signal’s dependence on the integration stages.

The strength of the delta-sigma (ΔΣ) architecture also happens to be one of its biggest limitations. ΔΣ analog-to-digital converters (ADCs) contain a large amount of digital circuitry¾in many cases more than 50% of the die area. The die can benefit from scaling a submicron CMOS technology, but only if the necessary analog structures remain available.

When developing leading-edge ΔΣ ADCs, process selection is very important for optimizing both the digital circuitry (area and power) and the analog circuitry (SNR and linearity). Lower voltages and smaller gate capacitances mean lower processing power for the digital sections, while scaling on the analog side is limited by the nature of the input signals to be measured.

Process features such as a high-linearity metal-insulator-metal (MIM) or poly-poly capacitor structures make it possible to fabricate low-noise, high-fidelity sampling networks suitable for memorizing analog information. Deep N-well structures enable sufficient decoupling of analog circuitry from the substrate background noise, and they supply vertical NPN transistors that are greatly needed for the amplifiers and references.

Architectural choice also plays a role in energy-efficient designs. Different modulator structures, which are basic to the operation of ΔΣ ADCs, enable a smaller swing of output voltage within the integration stages. In turn, the amplifier at the heart of the integrator can be smaller and thus be driven by a smaller current.

Among techniques available to the low-power designer, two of the most popular are feed-forward topologies and the multi-bit feedback approach. Feed-forward topologies can limit or eliminate dependence of the input signal on the integration stages. In the generic feed-forward implementation, choosing B(z) equal to 1/F(z) will eliminate the signal-dependent portion of the output (see the figure). Selecting these quantities so B(z) = F(z) = 1 will lead to the classic feed-forward topology.

Decoupling the integrator output swing from the input signal allows the system to accept a larger input signal without clipping. Larger input swings reduce the power requirement by permitting a higher noise floor at a given SNR.

If the system processes only the quantization error (especially when using multi-bit feedback), it can operate with less integrator linearity and lower gain bandwidth in the amplifier. Multi-bit feedback amplifies this effect even further by decreasing the voltage difference from one quantization step to the next. Such an action again reduces the power required in the amplifier, while still avoiding the slew-rate-limited region of operation.


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