Fig 1. Digital filters are just a combination of multiplications and accumulations. Shown are an IIR filter with feedback and an FIR filter with a series of weighted samples (taps).
Fig 2. Starting with a verbal explanation of a first-order filter, it is easy to draw a block diagram if you remember that z-1 means “previous.”
Fig 3. In a first-order /n sinc decimator, each new input is accumulated. After “n” samples, the result is subtracted (delta) from the previous values.
Fig 4. A second-order /n sinc decimator is constructed on the same principle as a first-order. This particular topology has been changed to only require a subtractor.
Fig 5. Modulators and filters are building blocks that can be combined to make many different circuits.
First, I would like to thank the readers who have sent me e-mails about this series. Most have been polite, and many have included helpful suggestions. From the questions I have received, it is apparent that many of you are starting to think of delta-sigma modulators as more than just the first half of an analog-to-digital converter (ADC).
I’m assuming that if you’re reading this, you have read the three previous columns in this series (see http://electronicdesign.com/author/2016/DaveVanEss.aspx). In short review, a modulator is a device that converts an analog or digital signal into a density stream, while a filter converts a digital stream to an analog or digital signal. The previous columns included examples of linear multipliers and adders, both analog and digital, as well as equivalent density circuitry.
There are two basic types of digital filters: infinite input response (IIR) and finite input response (FIR) (Fig. 1).
The top filter is a second-order IIR filter. It’s called that because the feedback guarantees that a small part of every input is part of the output. In fact, Alexander Graham Bell believed that sound only attenuated and never really went away. It was his goal to design equipment sensitive enough that he could hear the “Sermon on the Mount.”
The FIR filter is just a series of multiplies and accumulates with previously stored input samples (tap). Since there is no feedback, this type of filter cannot become unstable, and computational error won’t accumulate.
Now some people are uncomfortable with the z-1 term. Think of it as just meaning “previous sample.” As an example, suppose you wanted a first-order IIR filter that sums three quarters of the previous output with one quarter of the current input:
Substituting “previous” with “z-1” results in:
From this equation, we can implement the filter block diagram shown in Figure 2.
For further information on digital filters, I recommend “Implementing IIR/FIR Filters APR7” by John Lane and Garth Gilman of the previous Digital Signaling Processing Division of Motorola (see http://irtfweb.ifa.hawaii.edu/~m2/tony/DSP56000_ref/doc/appnotes/apr7.pdf). It is too big to call an app note and too small to be called a book, but it is free on the Internet. It is part of an excellent series of notes that includes PID control (APR5), ADPCM (APR9), and delta-sigma modulation (APR8).
Now a problem with digital filters is that they generally require a digital multiplier as large as 32 bits. One popular digital filter, the sinc decimator, is called that because its frequency response approximates a sinc (sin(x)/x) function. It is also called a boxcar filter because all the taps have the same weighting. I like to call it a sigma-delta filter for reasons that will become apparent in Figure 3.
The “n” samples are accumulated and then differenced with the previous value. Sigma delta! Although it may not have the best frequency rolloff, it is easy to construct. It only requires an adder for accumulation and a subtractor for differentiation.
Figure 4 shows a sinc2 decimator. For this decimator, the topology has been slightly changed to allow it to be constructed with subtractors. Equation 3 shows the frequency response, where “K” is the filter order and “n” is the decimation value.
The output rate will be 1/nth the sample rate. The important factors for specifying a sinc decimator include the sample clock (fs), the decimation value (n), and the number of stages (K). I find it conceptually pleasing that a delta-sigma modulator is coupled with a sigma-delta filer to construct an ADC.
Modulators And Filters
So far we have developed four different blocks:
• An analog modulator (Amod) that converts an analog value into a density signal
• A digital modulator (Dmod) that converts a digital value into a density signal
• An analog filter (Afilt) that converts a density signal into an analog value
• A digital filter (Dfilt) that converts a density signal into a digital value
These blocks can be arranged in many combinations (Fig. 5). If you combine an analog modulator with a digital filter, you get an ADC. It could be a second-order delta-sigma modulator followed by a SINC3 decimator. Combine a digital modulator with an analog filter, and you get a DAC. It could be as simple as a pulse width modulator (PWM) and a passive R-C filter.
If you combine an analog modulator with an analog filter, you get an analog-to-analog converter (AAC). Now this seems like a lot of work to convert an analog signal to an analog signal. Some of you may be thinking that you could replace it with some simpler circuit, like maybe a WIRE. Well, if you place a digital isolator between the two blocks, you’ll have an analog isolator.
In this way, for the cost of a digital opto-isolator, you can get an isolated analog signal. An inexpensive way to measure a high-side current shunt is to build a modulator that is referenced to one side of the shunt and bring the density value down to ground via some isolator so it can be filtered.
This is a good place to stop for now. In my next column, I will discuss more complex signal processing. Stay tuned!