Expect More Gas And Less Oil In Your High-Speed ADCs In 2011

Dec. 9, 2010
Analog Devices' Rob Reeder analyzes design tradeoffs between fab process geometry, ADC sample rate and resolution, analog input input bandwidth, EMI resistance and other characteristics and how they are affecting new chip designs.

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New applications and system strategies are moving onward, so the market outlook is good for converters in 2011, with lots of new opportunities for the industry to explore. The demand from customer applications is high and system knowledge is key in designing the right parts to win sockets.

With such high demands come some great challenges to both the IC manufacturer and the customer as well. These challenges continually push developments to be feature rich with lower power, while providing more bandwidth and faster speeds in the form of sampling and digital output data rates. Our friend performance needs to stay on track too with these new challenges.

The Road To 65 nm
Applications, both new and old, are increasingly demanding parts that suck less current from a power supply. Most applications today tout a portable and/or “Green Feel” to them, which in turn challenges the IC manufacturers. This push for lower power comes from our customers, and it naturally makes us move down in process nodes to reap those power benefits.

Only a couple of years ago, the industry moved from 0.35-um designs to 1.8-um technology, cutting power dissipation in half. Today, most users of this technology have a handle on the models/tools and the understandings of the current process, which has led us to design analog-to-digital converters (ADCs) in the sub-100-mW range, assuming a 12-bit, 65-Msample/s ADC. Designs now are on track to hit the 1-mW/Msample/s barrier.

The 65-nm move is on. Test chips are being deployed and many design initiatives are starting to use this process. This will allow us to scale the power down even further and pack more features into smaller spaces. The price everyone pays is that power-supply voltages will have to go down from 1.8 V to 1.2 V. For lack of a better term, 65-nm devices are “gain challenged” compared to 0.18 mm, and a 65-nm mask set is pricier too.

This brings forth new challenges for IC designers to maintain speed and dynamic range. So, you have to instill some confidence when working with any new process to understand all its tradeoffs with the need to learn its models and tools to build a solid design.

Lastly, 65 nm naturally gives rise to faster speeds, i.e., fast rise times, which are the real reason for not stopping at 110 or 90 nm. As you move down the lithography curve, junction parasitics within the devices inherently become, well, less. This can either help or hinder the design depending on how speed is used.

For example, if the particular design is being developed solely to hit gigasample-per-second speeds, then a 65-nm process has its advantages. However, a low-power focused design might not want this inherent feature because of certain electromagnetic interference (EMI) constraints given the lower threshold regions.

More Bandwidth Please…
The demand for analog input bandwidth is going up too. From the converter standpoint, you can look at this in two ways. Some customers want to sample at really high frequencies—yes, 500-MHz IFs and beyond. This means the converter needs to be able to settle faster while maintaining linearity.

Bandwidth can also be seen as the amount of bandwidth or the frequency user band for the application. Communication infrastructure is roadmapping itself into larger bandwidths suggesting 100 MHz or more in the coming years to allow for multiple carrier technologies to be deployed within a single design.

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The other advantage to higher IF sampling is still true too; the higher the IF the ADC can sample, the fewer constraints it puts on the entire signal chain and filtering, meaning fewer components to be dealt with. This ultimately gets you closer to the antenna—Yip, RF to bits.

Therein lies another challenge, the front-end design. Internally the ADC must maintain very good linearity. The same is true externally. Active (amplifiers, demods, and mixers, oh my!) and passive technologies (transformers) need to be better at maintaining high linearity past 500 MHz as well, which means +85-dB spurious-free dynamic range (SFDR).

The front end needs to be easy to drive and have low input gain (<7 dBm to reach full scale), low noise (+74-dB signal-to-noise ratio, or SNR) and good passband flatness (~1 dB). So in the end, it is a two-part challenge. My guess is this latter challenge will take some time to perfect as well. Stay tuned.

You Want Me To Capture What?
With the advent of faster sampling clock rates, the data inherently follows. With that, higher data rates are pushing the boundaries into new techniques for packing, sending, and receiving data serially. Thus, we come to the JESD204A and B standard definitions. The definition was constructed to support various bit widths, sample rates, and channel counts that have data rates of 4.2 Gbytes/s max for one serial link.

The transmitter emits a continuous, 8B/10B encoded data stream that uses specified symbols for synchronization over 20 cm of copper traces on standard FR4 material. The interface logic preferred is current mode logic (CML), which is a form of low-voltage differential technology specified with a 1.2-V common mode.

For example, if we have a 12-bit ADC that is sampling at 210 Msamples/s, the serialized output data rate would be 4.2 Gbytes/s for a 16-bit link. This translates into 60% link efficiency with 20% overhead for over-range and other control information and 20% overhead for 8B/10B encoding.

These definitions deploy the screaming data in a packetized manner that requires fewer ADC pins. The advantages here are less board space and routing between the transmitter and receiver because only two pins are required on either side per ADC channel. The downside is that the receivers have to be “special” and are usually limited in number on the FPGA receiver.

These FPGAs are generally more expensive too. So for large systems that require multichannel counts, weighing the cost between FPGA resources and simplistic routing is usually up to the digital designer. Typically the designer is fighting to save pins on the FPGA rather than give them away to parallel bussed converters.

2011 Wrapup
High-speed converters are always seeing a continuous uptick in the number of applications that need slick solutions that provide a direct impact on the overall system. The converter development business is healthy today and will continue to be past 2011 with so many applications in communications, instrumentation, and healthcare. This in turn pushes our engineering teams to become creative and come up with new methods and technology breakthroughs to serve those opportunities and challenges.


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