Electronicdesign 5655 Vaness595x335

Integrate Your Signals Before Digitizing Them

Oct. 5, 2012
Heuristic derivation of a circuit that does not require an ADC to digitize the integral over time of an input signal.

As an applications engineer for a company making configurable analog products, I occasionally get asked to provide a design to integrate a signal before digitizing it. In many cases, the people doing the asking are interested in the area under the waveform. Sometimes they just want to use the integrator to amplify a very small dc signal. They initially envision a resettable integrator followed by a sample/hold (SH) that feeds a successive approximation register (SAR).

The op-amp circuit in Figure 1 is an inverting integrator. The switch across the feedback capacitor is used to discharge it and zero the output. When the switch opens, the input signal is integrated, and its output is determined by:

1. In a classical integrating ADC, the integrator is held in reset until the signal sample is started. The integration is completed with the capture of the integrated signal.

The output voltage is determined by the values of the input signal, the integration time, and the values of the passive components. For a dc input, this equation simplifies to:

Control signals are required to take the integrator out of reset, capture the value of the integrator’s output, and trigger the analog-to-digital converter (ADC). I immediately show them a simple cost-reducing alteration (Fig. 2). Adding a switch to the input allows it to be disconnected from the integrator. With no more input, the integrator holds the value, and the discrete SH is no longer necessary.

2. The addition of an input switch allows the sample/hold (SH) to be incorporated into the integrator, and the external one can be removed.

Suppose you want to integrate a 20-mV signal for 30 ms. This works out to 600 mV-s. Suppose the ADC has a ±1-V input range. If a capacitor value of 4700 µF is selected, to keep the output within 1 V the resistor must be at least 128 kΩ. Selecting a resistor value of 150 kΩ produces an integrator output voltage, after 30 ms, of:

This fits comfortably in the range of the ADC. At this point, I recommend using a capacitor with low dielectric absorption since 30 ms is a long time to keep a charge on a capacitor. To make sure that some charge isn’t absorbed, use a polyester or polycarbonate capacitor (see “Using Delta-Sigma Can Be As Easy As ADC, Part 2”). So, you have a solution that requires an integrator with an expensive capacitor, a couple of switches, an ADC, and some hardware signals to control it. But there’s a simpler way.

A Different Approach

Instead of continuing to store the charge on the capacitor, suppose you precisely remove it and keep track of the amount that has been removed. If the input voltage is positive, a current is pushed into the cap and the inverting integrator output goes negative. For a negative output, if a precise amount of charge is pulled out of the cap, then the output moves back toward zero. Do this continuously and no long-term charge is stored on the capacitor, enabling a less expensive capacitor to be used. The circuit in Figure 3 can be implemented with an inexpensive 7XR ceramic capacitor.

3. By monitoring the polarity of the integrator output, it’s possible to push or pull a quantum of charge to move the integrator’s output back toward zero.

As with Figure 2, there is an inverting integrator. However, negative feedback has been added. A positive input causes the output of the integrator to move negative. When below AGND (Vdd/2), the comparator switches low. Latching this value with a flip-flop guarantees that –0.5 Vdd, referenced to AGND, will be applied to the feedback resistor for a fixed time of one period.

A reference of the opposite polarity of the input is fed back to the integrator, causing the output to move back to the center. A negative input causes a positive output on the integrator, in turn causing a positive reference to be fed back. This circuit is still an integrator except now the charge is removed from the capacitor precisely.

Since it is precisely measured, this information can be used to determine the total amount of charge originally placed in the integrator. If you run it for an integration time of “n” cycles of a sample clock (fs), the input will be integrated for n/fs seconds. If DOut is high for “m” of those counts, then a negative reference (–0.5 Vdd) is fed back for a time of m/fs seconds. If DOut is high for m counts, then it must be low for n-m counts, causing a positive reference to be fed back for (n-m)/fs seconds. The output of the integrator is:

By keeping track of the values “n” and “m” and measuring the output of the integrator, you can calculate the average input voltage. Suppose, like before, you want to integrate a 20-mV signal for 30 ms with a 250-kHz sample clock and a 5-V supply. This means you would want to run this integrator for 7500 cycles.

The RC timing value is set so the integrator output, caused by the input signal, moves no more than 1 V. This value is determined by the slew rate limitation of your op amp. Lower the value if your op amp has a lower slew rate, but remember, less gain in the integrator requires more sensitivity in your comparator. Given these parameters, the RC time constant is:

Meet this requirement by setting the integration cap to 47 pF and the input resistors to 1.74 kΩ. The feedback can only change the output by the same amount. Given all the other values, the value of the feedback resistor is determined by:

If the integrator had no feedback and no supply rails, its output after 30 ms would be over 7000 V. With feedback, the integrator’s output voltage is guaranteed to be within ±0.5 Vdd and can be considered an insignificant residue. Knowing this, Equation 4 simplifies to:

This ADC has a usable range of ±20.7 mV. Its resolution is determined by the number of cycles it is operated. Increasing cycles increases resolution. To increase the range, just increase the input resistance. What is really sweet is that since the feedback removes the charge from the capacitor, you don’t have to provide reset circuitry. Figure 4 shows a variable length integrator:

4. By measuring the total number of counts with one counter and those that are high with the other, it’s possible to measure the average input voltage.

With the addition of two counters, it’s possible to measure the total number or cycles as well as the number where the logic output is high. To operate, start the integration and trigger at the desired start time. This trigger will latch the present values of the counters and generate an interrupt. This interrupt will allow your microcontroller to record the values of the two counters. (Call then m0 and n0.) Trigger it again at the desired stop time, and let the microcontroller collect the counts (m1 and n1). The average voltage is:

If you require the area under the curve, just multiply the total number of cycles and the time each cycle takes:

So, it’s possible to digitize an integrated input using only an integrator, a comparator, a flip-flop, a feedback resistor, and a couple of counters. No other ADC is needed, though you may suspect that this is just a delta-sigma modulator (DSM) with a SINC digital filter. A DSM allows more of the signal processing to be completed with simple logic, and it can greatly reduce the cost of your circuitry.

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