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Partial Fallback to Analog May Help Smart Pacemakers Run Longer on a Battery Charge

Feb. 25, 2014
For use in pacemakers, a new analog signal processor (ASP) utilizes an analog feature extractor (FE) to consume minimal power.

Smart Pacemakers may get smaller thanks to that involved both the Low Countries and Toshiba.

At the International Solid-State Circuits Conference (ISSCC) in January, researchers from IMEC in Belgium, the Catholic University of Leuven, Belgium, the Technology University of Eindhoven in the Netherlands, and Olympus Corporation in Tokyo, described a tiny, ultra-low-power analog signal processor (ASP) for heart-rate monitoring in implantable pacemakers. (See figure above.) Pacemakers need such functionality to sense cardiac rhythm disorders.

Essentially, the ASP executes a DSP function to extract the timings of three points: Q, R, and S, in the electrical signature of each heartbeat. (i/e., the signature of the heart itself, not the timing pulse from the pacemaker.)

To reduce power consumption, the team shifted the functionality of QRS-band power parameter extraction to the analog domain.  They also developed a current-multiplexed ADC driver and a flexible ADC. As a result, the power consumption of the ASP is less than 1μW. This had little or no effect on ac performance, with SNR less than 70 dB, CMRR less than 90 dB, and PSRR below 80 dB.

The paper, “680nA Fully Integrated Implantable ECG- Acquisition IC with Analog Feature Extraction” is from ISSCC-2014 Session 24.

About the Author

Don Tuite

Don Tuite writes about Analog and Power issues for Electronic Design’s magazine and website. He has a BSEE and an M.S in Technical Communication, and has worked for companies in aerospace, broadcasting, test equipment, semiconductors, publishing, and media relations, focusing on developing insights that link technology, business, and communications. Don is also a ham radio operator (NR7X), private pilot, and motorcycle rider, and he’s not half bad on the 5-string banjo.

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