1. This optimised analogue-conditioning circuit can avoid signal distortion caused by nonlinearities, and guarantee an optimum interface between the encoder and ADC.
2. shown is a normalised RC filter transfer function with 20% mismatch in CF between sine and cosine channels.
By Juliano Vidi
High-performance motioncontrol systems require high dynamics, speed, stability, and rigidity, which can only be reached with ever-increasing gain factors in the control loops. High control gain combined with low accuracy and low-resolution position/speed feedback information cause speed instability, noisier behaviour, and higher driving currents.
Consequently, additional heat generation in the driver and motor may be observed, caused by elevated power losses. This reduces energy efficiency and doesn’t allow the motor to achieve its maximum mechanical power rating.
A number of techniques are available to minimise the effect of weak feedback positioning systems. However, most of these don’t improve the performance at low speed. Some of them need additional hardware or higher computing performance, which usually results in higher system cost. In addition, the time delay caused by digital filtering and processing must be kept to a minimum, otherwise it will reduce the control bandwidth and may ultimately compromise dynamic accuracy.
To avoid poor motion-control performance and reduce the demand for complex signal processing, the feedback system must be able to deliver highly accurate information with high resolution. To perform positioning and speed measurement, optical and magnetic encoders with sinusoidal outputs are suitable options for delivering higher accuracy and resolution.
High-resolution encoders usually have between 512 and 8192 sine/cosine periods per mechanical revolution (1 turn). Moreover, it’s possible to multiply encoder resolution by 512, 1024, or even more than 2048 times using interpolation techniques. A common method is direct arctangent computation, where the sine and cosine signals are sampled with analogue-todigital converters (ADCs) to execute further processing.
For noise immunity, sine and cosine are typically differential signals with amplitude between 0.8Vp-p and 1.2Vp-p. In many cases, there’s a dc offset between 2V and 3V.
Inaccurate analogue-signal conditioning affects the results of arctangent calculation, thus requiring additional advanced digital processing to compensate for the errors. The three major degradation factors—offset error, gain mismatch, and phase difference—must be kept at very low levels to ensure that the needed accuracy and performance is achieved.
To minimise these errors and make the signals more robust against noise, amplification and filtering is required. To avoid signal distortion due to analogue circuit nonlinearity and guarantee an optimum interface between the encoder and the ADC, the proposed analogue- signal conditioning should do the trick (Fig. 1).
Basically this configuration amplifies the differential signal, eliminates the inaccurate dc offset coming from the encoder and introduces an accurate level shift to the differential signal (VLS). Sine and cosine are sampled simultaneously to avoid any phase errors. The supply voltage is 5V and can be used to supply the encoder as well, since most of the available sinusoidal encoders operate in the powersupply range of 3V to 14V.
The chosen analogue to digital converter is the dual 12bit, 50-to- 200ksample/s, simultaneous sampling ADC122S625. Due to the device’s energy efficiency, it’s become a member of National’s PowerWise family.
The ADC is based on a successive- approximation-register architecture, whereby the differential nature of the analogue inputs is maintained from the internal track-andhold circuits throughout the device to provide excellent common-mode signal rejection.
The ADC122S625 features an external reference input that can be set to a 1.0V minimum and the supply voltage as a maximum. The ADC122S655 and the ADC122S706 may be used if sample rates from 500ksamples/s up to 1Msample/s are needed.
The level shift (VLS) is a commonmode voltage introduced to the differential signal. The advantage is that it needs only a single-ended power supply and the level-shift voltage will be eliminated directly at the ADC differential inputs.
With the eventual goal of optimised board space, ADC-input dynamic range, and minimised costs, one precision voltage device provides the same voltage for level shift (VLS) and ADC reference (VREF). If VLS = VREF = 2.5V, the achieved input dynamic range is VLS ± VREF, i.e., from 0 to 5V.
Another advantage is that initial accuracy and temperature drift aren’t critical for level shift and reference voltage when using this circuit. First, because the VLS is a common-mode voltage, even its variations at low frequencies are eliminated at the differential inputs from ADC. Secondly, the reference voltage for both ADC channels is the same, and possible variations cause gain changes in both channels equally, thus avoiding any possible gain mismatches.
On the other hand, the reference voltage must be a very low noise part, because high-frequency common-mode voltage noise isn’t rejected well at the ADC-differential inputs. As a result, the PowerWise series voltage reference LM4140, replete with its 2.2µVp-p noise level, can be used as VLS and VREF. Therefore, it becomes an ideal choice in this case.
SIGNAL LINEARITY, DYNAMIC RANGE, AND SLEW RATE
The differential signals must be amplified in order to improve their robustness against common-mode voltage noise as well as maximise the ADC-input dynamic range utilisation. In theory, the amplified signals could swing from ground to amplifier supply voltage to profit from the full code range of the ADC. However, even if many operational amplifiers are able to work rail-to-rail nowadays, there are physical limits, which don’t permit the extension of the op-amp-output dynamic range to the rails without losing some percentage of signal linearity (distortion).
Good precision amplifiers usually have much less than a 100mV output swing limitation from either rail. In our case, the 5V power supply and 2x100mV total output swing limitation allows 4.8Vp-p output dynamic range. Bearing in mind the input differential signal may reach 1.2Vp-p, the recommended gain for guaranteed linearity and maximised code utilisation is 4 (4.8Vp-p/1.2Vp-p).
Another important parameter for maintaining the signal linearity is the amplifier minimum slew rate. Low slew rate deforms a sine wave to triangular-shaped signals. The maximum sine-wave frequency (fMAX) sustained by an amplifier without causing distortion is a function of the peak amplitude (VPP) of the output and the amplifier minimum slew rate (Sr).
The PowerWise dual-precision amplifier LMP7716, selected for this application, was chosen based on its low noise, low offset, low input bias current, high gain bandwidth, and a guaranteed minimum slew rate of 6V/µs. This permits, in the worst-case scenario, the measurement of distortion-free signals up to 200 kHz.
CLOSED-LOOP STABILLITY AND PHASE ERROR
For enhancement of closed loop stability, capacitors CF are added to the feedback path. In addition, CF with RF builds filters that minimise the effects of differential noise at high frequencies. However, with the erroneous hope of noise cancellation at low frequencies, the filter cutoff frequency (fc= 1/2p × RF × CF) is very often placed close to or even inside the signal frequency range (200kHz in our case). Given that, noise and signal would be attenuated in the same ratio (SNR stays constant). The filtering at low frequencies is not only ineffective, but it could introduce phase errors between the channels because standard capacitor tolerances tend to be quite high.
Figure 2 illustrates the phase error due to capacitance mismatch between CF in the sine and cosine channels. The red curves represent phase and gain of an RC filter and the blue curves represent a shift in the face of capacitance variation. Phase error between channels up to 5.74° may occur close to the cutoff frequency (fc) if capacitors with ±10% tolerance are used.
Thus, it’s recommended to place fc about one decade higher than the maximum signal frequency. Consequently, the input signal operates in the green highlighted frequency region, where the phase error is much smaller, even with big capacitance mismatches. With CF = 10pF and RF = 10kO, then fc ˜ 1.6MHz.