Intel is expanding its New Mexico operations to manufacture new generations of chips based on its Foveros 3D packaging technology, a move that could aid the company’s attempts to regain its leadership status in the semiconductor industry.
Intel said it would invest $3.5 billion to scale up its Rio Rancho fab and boost its headcount by more than 35% at the sprawling complex, one of its three largest US manufacturing plants, with the others located in Arizona and Oregon. Intel is now in the planning phase and intends to start building in late 2021. The company said the fab would be set for production by late 2022, ahead of releasing its first 3D CPU based on Foveros.
For Intel, this is its latest major investment in its manufacturing operations under chief executive officer Pat Gelsinger, who was appointed at the start of the year to overhaul Intel's strategy as it grapples with delays in its most advanced CPU production. In March, he announced Intel's new "IDM 2.0" strategy that he said would help it regain the manufacturing prowess that it ceded to TSMC and other chip rivals in recent years.
One of the company's new strategy pillars is expanding its internal manufacturing capacity. Intel is investing $20 billion to construct a pair of fabs in Arizona, where it will manufacture advanced chips as well as compute tiles—what industry insiders also call chiplets—that can be assembled with Foveros or other advanced packaging tools. It is eyeing subsidies from the US government to expand its footprint further.
Intel also plans to outsource more of the chips at the heart of its product portfolio—including a wide range of compute tiles based on advanced process nodes—to TSMC, Samsung, and other outside foundries. It has also established an independent foundry business called Intel Foundry Services—IFS, for short—that will take advantage of its vast manufacturing operations to mass-produce chips for other firms, even rivals.
Intel plans to use the new investment to gain more scale as it expands into making more products out of compute tiles. Foveros is a type of advanced 3D packaging that lets Intel roll out processors by stacking compute tiles like the floors in a microscopic skyscraper, offering more performance in a smaller area. The tiles are lashed together with silicon wires that serve as elevator shafts between different floors.
Intel plans to roll out its first flagship central processing chip for personal computers based on Foveros, code-named Meteor Lake, in 2023.
Intel has been investing in Foveros and other tools in its advanced packaging arsenal as it faces longer delays in developing its most advanced chips based on the 7-nanometer process. Intel is moving from monolithic systems-on-a-chip (SoCs)—where all the parts of the IC are crammed on the same die and all based on the same process node—to systems in package (SiPs) that are patched together out of pre-made chips.
That gives Intel the freedom to mix and match compute, memory, and other semiconductor tiles—potentially based on different process nodes—all in the same package, paying major dividends in performance and power efficiency that it is struggling to wring out of smaller transistors. Intel said it could use different combinations to maximize power efficiency, cost, or other features of chips designed for areas such as 5G.
Intel currently develops and manufactures a wide range of technologies at the Rio Rancho fab, including its Optane memory and silicon photonics. It is also focused on its embedded multi-die interconnect bridge, or EMIB, which is used to scrunch together different silicon die side by side in the same advanced package. The way EMIB technology works, the final product resembles a compact circuit board (PCB).
EMIB uses a small silicon bridge embedded in the substrate under every compute tile, or other semiconductor die, packaging them all on the same horizontal plane. All the tiles communicate over Intel's advanced interface bus, or AIB, which serves as a die-to-die interconnect. Intel's AIB enables the compute tiles and other parts to act as though they are all on the same die without ceding too much performance.
The use of Foveros and EMIB also lets Intel use different production processes, whether from its internal fabs or outside foundries, for different tiles depending on its requirements. The vendor has previously said it plans to expand its relationships with many of the world's top foundries, ranging from TSMC and Samsung to UMC and Globalfoundries, as it builds more of its core products out of compute tiles.
That is a unique advantage that allows it to use best-in-class production processes for varying tiles. If it falls behind other foundries in the development of advanced process nodes—or other foundries roll out special-purpose processes that it wants to leverage—Intel can outsource the IP's production. Then it combines the internally and externally produced tiles with Foveros and sells the final package to partners.
Instead of locking Intel into a single production process from a single foundry, Foveros gives it the flexibility to use its internal 7-nanometer process (or the 5-nanometer node at TSMC) in its central compute tiles and integrate it with non-compute tiles based on its 28-nanometer node (or the 14-nanometer node from GF), where scaling the transistors can hurt more than it helps. Legacy nodes also tend to cost less.
There are economic advantages, too. These interchangeable slabs of silicon have a smaller footprint than a full system on a chip, leaving less space for imperfections, abnormalities, or other faults. That improves the yield or the fraction of chips that are not discarded during the production process. Using outside fabs could also help prevent future shortages and other manufacturing snags.
Intel has previously used its Foveros technology in its "Lakefield" chip for personal computers. The ultra-compact chip is based on a combination of large high-performance "Sunny Cove" CPU cores and smaller high-efficiency "Tremont" cores housed on the same 10-nanometer compute tile. The heterogeneous CPU is stacked on top of a separate 22-nanometer tile that contains all the industry-standard IO.
Intel is also using EMIB in combination with Foveros to roll out other chips currently in production, including the “Ponte Vecchio" server processor for use in the Aurora supercomputer in the US. The chip incorporates more than 40 heterogeneous compute tiles—what Intel termed XPUs—many based on Intel's 10-nanometer node and other processes. TSMC and other outsiders make the other tiles.
The other advantage of Foveros is that it increases die area—including all the compute tiles—of the final chip beyond what can be manufactured in a single slab of silicon, which is constrained by the reticle limit of the fab. Ponte Vecchio has more than 100 billion transistors, compared to about 54 billion transistors in Nvidia's most advanced graphics processing chip, which uses the 7-nanometer node.
“Our Rio Rancho campus is an important part of Intel's global manufacturing network,” Keyvan Esfarjani, Intel's SVP and GM of manufacturing and operations, said at a press conference last Monday. “And with today’s announcement, our New Mexico operations are more even more critical and vital to Intel’s success."
Intel currently employs 1,800 workers at its Rio Rancho fab, and the new investment will bolster that total with 700 new jobs. Intel said the improvements would yield 1,000 construction jobs and 3,500 additional jobs within the state.