Intel is racing to regain its footing as the unquestioned leader in chip manufacturing technology by 2025.
The Santa Clara, California-based company recently released one of its most ambitious roadmaps in years, full of new process and packaging technologies that Intel argues will close the performance gap with rivals by 2024 and give it process technology leadership by 2025. The goal is to roll out a newer generation of processors—and a new process node to mass-produce it—every year through 2025.
Every generation of processors will be based on more advanced transistors than the last. Intel said that it is bringing features into the fold at every stage of the roadmap, including a new transistor architecture called RibbonFET by 2024 and a new interconnect system called PowerVia the same year. It is also expanding the use of EUV lithography at every node and plans to beat its competitors out of the gate with "high-NA" EUV.
The company revealed the new process and packaging roadmap at its “Intel Accelerated” event last month.
Intel has slipped from the leadership spot in the semiconductor industry in recent years. Behind Intel’s woes is a series of manufacturing missteps that forced it to delay its most advanced processors for data centers and personal computers. In February, Intel hired its former chief technology officer Pat Gelsinger as CEO to reinvigorate its chip development process and regain ground being surrendered to a growing crowd of rivals.
Because it dragged out the development of its 10-nm node for years, Intel fell behind TSMC in its ability to mass-produce the most advanced chips. TSMC has beaten it to the broader market with its 7-nm node and then jumped ahead to another generation with its 5-nm process, which was first adopted by Apple. TSMC is the world’s largest chip foundry with more than 500 customers, including many of Intel’s leading rivals.
Prolonged delays have opened the door for a growing horde of rivals including AMD and Arm to dent Intel’s dominance in personal computers and data centers. Intel's collapse has raised questions about whether it would expand its use of foundries—or dismantle its manufacturing operations in favor of outsourcing more of its production—to keep it from falling further behind rivals and losing more orders from Apple and AWS.
But Intel doubled down on its manufacturing business with the announcement of its IDM 2.0 strategy, which will see the Silicon Valley giant keep most of its production in-house and invest tens of billions of dollars in its semiconductor fabs.
One of the pillars of the turnaround plan is expanding its manufacturing operations, starting with $20 billion to build out its U.S. fabs, giving the company the capacity to meet its own needs and mass-produce chips under contract for other firms and even rivals. Intel also formed a foundry business unit, called IFS, and eyeing a ramp-up of its foundry use, including for some of its most advanced processors starting in 2023.
But at the heart of the strategy is an aggressive rebuild of Intel’s manufacturing prowess. "Building on Intel’s unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we're on a clear path to process performance leadership by 2025,” Gelsinger said. "We will be relentless in our pursuit of Moore’s Law."
Intel is also adjusting the nanometer-based node nomenclature that the semiconductor business has used for decades. The company will rename its process nodes to better align with industry standards.
Today, the most advanced processors have up to tens of billions of transistors serving as tiny electronic switches that control the flow of current. Every transistor contains a gate mounted on top of the channel that current travels through, bridging the "source" and "drain" sides of a channel. A gate is used to control the current traversing the channel and determines whether the transistor is in an “on” or “off” state.
For years, the gate was the most important dimension for determining the performance of a transistor, and the number of a process node corresponded to the dimensions of the gate or other parts of the transistor's anatomy. Even though Intel has continued to use numbered nodes based on the nanometer, the names no longer refer to the length or width of the gate or any of the transistor's other internal components.
Today, transistor density is the metric used by experts to compare different nodes. Intel has long argued its process technology can match or beat the performance of nodes numbered the same way from TSMC and other rivals in terms of the density of transistors that can fit on a square of silicon. According to industry analysts, Intel's 10-nm node is roughly on par with TSMC's 7-nm process in transistor density.
Intel said the new node-naming format will deliver more clarity to customers, including potential clients of its foundry business, and help them understand how the new process technologies stack up against rival nodes. Ann Kelleher, Intel's SVP of technology development, said the new names give more weight to metrics such as performance, power efficiency, and area while factoring in transistor density.
The new roadmap runs through the four technology nodes Intel plans to roll out after its 10-nm "SuperFin" node, which is used in its new generation of mobile processors, code named "Tiger Lake," introduced in 2020.
“Intel 7” is what the company plans to call its 10-nm “Enhanced SuperFin” process, which will be used to roll out its “Alder Lake” personal-computer processors in the second half of 2021 and “Sapphire Rapids” CPUs for data centers, which are on pace to be in production in the first quarter of 2022. Intel improved the FinFET transistors to bring a 10% to 15% boost in performance-per-watt over its previous SuperFin node.
Intel said the “Alder Lake” CPUs are currently in mass-production with the Enhanced SuperFin node, which wrings out another Moore's Law of performance from the 10-nm node to warrant using the “Intel 7” name.
"Intel 4" is the technology node formerly known as the 7-nm process, which Intel was infamously forced to delay out to 2023 due to defects in the production process. The company previously said that its future “Meteor Lake” CPUs would be assembled out of compute tiles based on the 7-nm node. The node would take full advantage of EUV to imprint smaller transistors on silicon wafers using ultra-short wavelengths of light—and in a way that reduces the risk of imperfections that can ruin the final product, improving yields.
Intel said that the node would have 20% more performance-per-watt than its predecessor on the roadmap, as well as area improvements. According to the company, it would be ready by the second half of 2022 so that chips would start shipping in 2023, including its “Meteor Lake” CPUs for the personal-computer market and its “Granite Rapids” CPUs for data-center servers. Test chips are currently in the lab.
“Intel 3” is what Intel previously called its 7-nm+ node, its final technology node based on FinFET transistors. Intel said it would start rolling out chips based on the node by the second half of 2023, delivering around 18% better performance-per-watt. The "Intel 3" node brings more advanced transistor technology into the fold and a high-performance library to assist in area scaling. Intel is also expanding the node’s use of EUV equipment.
Intel is leaning on its 2.5D and 3D advanced packaging arsenal to help close its performance gap with rivals. It also introduced new versions of its Foveros 3D chip-stacking technology set for mass-production by 2023.
The final stop on the new roadmap is the "Intel 20A" node, which the vendor said would open the door to the "angstrom era" when it is used to manufacture chips in early 2024. The "A" in the node stands for "angstrom," or one tenth of a nanometer. Previously known as the 5-nm node, Intel said 20A would take advantage of its RibbonFET and PowerVia technologies to bring it to “parity” with future nodes from TSMC and Samsung.
The RibbonFET is Intel’s first new transistor architecture since it introduced the FinFET a decade ago. A FinFET is formed by applying a fin-shaped flange of silicon to connect the source and drain sides of the channel in the transistor. The gate—the region that determines whether the transistor is turned on or off—is draped over the fin, surrounding it on three sides. This architecture helps reduce power leakage from the transistor. These tiny switches can turn on and off faster and waste less power than planar transistors.
The FinFET has been the workhorse in advanced chips for the last decade of Moore’s Law. The RibbonFET and other gate-all-around transistors promise to cram more performance in a smaller area without sending power requirements through the roof. In RibbonFETs, the fin is flipped on its side so that the gate surrounds the ribbon-shaped channel on all sides, preventing additional power from leaking out. Intel said these types of transistors offer faster switching speeds at the same drive current as multiple fins in a smaller footprint.
Intel said PowerVia is the first “backside power delivery” system. Today, the most advanced logic chips contain billions of transistors covered by a layered canopy of interconnects of varying dimensions that supply signals and deliver power between them. The interconnects are formed by carving tiny trenches out of a wafer, coating them with cobalt and other metals, and plugging them in with copper wires.
The problem Intel is trying to address with PowerVia is that the wires relaying signals and power are tangled together in the same stack of interconnects. But with PowerVia technology, the wires sending power around the chip are placed behind the transistors on the backside of the wafer. Thus, power can now be delivered directly to the transistors rather than traveling a longer distance through floors and floors of interconnects.
By relocating these wires to the other side of the wafer, the PowerVia technology frees the wires on the front side of the wafer for improved signal routing. The results are better power efficiency and higher frequencies.
The semiconductor giant is also early in the development on the “18A” process node, which is targeted for production in the first half of 2025. Intel said that it plans to improve the RibbonFET transistors at the heart of the process node, resulting in another major leap in performance. Intel said the 18A node is on pace to be more advanced than future nodes from TSMC, returning it to process technology leadership.
Intel has also partnered with semiconductor gear vendor ASML on the development of new high-numerical aperture (NA) EUV tools that can scorch smaller transistors into chips faster and more efficiently than the EUV technology in use today. Intel said that it expects to get the first production high-NA EUV tool in the industry and use it on its production lines by 2025 or later.
Despite the ambitious pace of its new process technology roadmap, Intel is playing catch up. TSMC has started supplying chips based on its 5-nm technology, while some customers are early in development with chips based on its 3-nm node. That means AMD, Nvidia, Qualcomm, Xilinx, and other chip companies can continue ordering chips that are more advanced than Intel’s—and they should be able to for at least three more years.
Obviously, as chip-making become more expensive and technologically tough, Intel's new roadmap is not guaranteed.
But the technology industry is not counting out Intel yet. The company said that it has landed Qualcomm as its first foundry customer for the 20A node due out in 2024. It also announced that Amazon AWS has agreed to adopt the advanced packaging technology Intel plans to open to customers of its new made-to-order chip business.