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RISC-V Meetups: In-Person Learning About the RISC-V Ecosystem

April 29, 2020
In these meetups, discover RISC-V software tools that you may even learn to “love.”

Interested in knowing more about RISC-V, the fast-growing open ISA specification? One way is to attend a local meetup. These events are being held all over the globe. A meetup is an in-person gathering coordinated via the website. The site contains a wide array of topics and only a small fraction are technical. The RISC-V Foundation is using meetups as a way to connect on a personal level. These events are also a social gathering with learning in an informal setting. This grass roots effort is very effective in spreading the awareness and learning about the latest in the RISC-V Ecosystem.

Western Digital was the first RISC-V member company to create a RISC-V Meetup group. Today, there are 18 locations, with more being added regularly. To see if a RISC-V Meetup group is in your area, head over to the website and search for RISC-V. Popular locations include the Bay area, Tokyo, Austin, Seattle, San Diego, Toronto, Munich, Pune, and many more. Not only are RISC-V meetups an opportunity to learn about the latest technology offerings, they’re also a social event to meet industry workers, conduct business, explore job opportunities, etc. 

At a recent bay area RISC-V meetup held on Feb. 13, four organizations participated. This event was focused on software tools for RISC-V users and device designers. IAR Systems, OneSpin Solutions, Ashling, and Antmicro were the companies that presented.

This meetup was typical in that the setting was informal; there were many questions and discussions during and after each presentation. The event started out with a brief update on the RISC-V Foundation. Highlights included a forecast prediction of 62 billion RISC-V cores to be shipped by 2025, with the industrial section leading at nearly 17 billion cores. The RISC-V membership has now surpassed 490 total members with over 200 organizations of various types in the group. Next up was IAR Systems.

IAR Systems

As the leading commercial tools vendor for RISC-V, IAR Systems aims to provide a stable and future-proof tool suite as well as global technical support. The IAR Embedded Workbench toolchain for RISC-V was explained as well as a demo of the software and I-jet trace and debug probes. The IAR C/C++ Compiler is a platform that’s optimized for the various RISC-V architectures. Currently, all of the released 32-bit extensions are supported. These are often shown as RV32IMAFDC,E.

Work is underway to support newer extensions, with plans to support 64-bit cores. The debug and trace capabilities enable you to find functions that are consuming more time, so code optimizations can be performed quickly. Click here for IAR Systems’ presentation.

OneSpin Solutions

The next presentation was from OneSpin Solutions. This company provides formal-verification tools for RISC-V Cores. What was memorable from this presentation were the bugs that their tools found in some open-source RISC-V cores. It was explained that RISC-V cores are challenging to verify because there are many optional instructions; complex micro-architectures are permitted, not to mention custom instructions.

The OneSpin Formal Verification tool provides complete coverage and guarantees full compliance to the RISC-V ISA and privileged ISA. OneSpin ran the open-source cores RI5CY and Rocket through its tool. Both designs had more than five issues, which were reported to the developers.


Ashling’s presentation would win the most creative award. The company played on the theme of loving their toolset because it was the night before Valentine’s Day. Ashling’s key message was that they have both software and hardware expertise. Their RiscFree offering provides a multicore heterogeneous solution with a single tool chain and probe.

RiscFree is an Eclipse-based IDE for RISC-V and other types of cores. An example heterogenous design was shown with a multicore SoC that contained both Arm and RISC-V cores. RiscFree is able to debug with a single interface and each core’s registers could be viewed in separate windows. Ashling concluded by mentioning its TaaS (Tools as a Service), where they customize the toolset for your device, including supporting customer RISC-V implementations. Certainly a lot to love.


Last up was Antmicro’s presentation. The company provided an overview of the open-source tool called Renode. Antmicro is on the front lines helping companies realize the promise of RISC-V. Renode is a flexible, configurable simulator that runs on numerous platforms. It can mimic a device or an entire board. Full debug capabilities are included via GDB support.

A notable RISC-V example that can be run on Renode is the Microchip PolarFire SoC. It’s a five-core RISC-V CPU complex capable of running Linux with a full peripheral set, including a FPGA fabric. Antmicro also shared that TensorFlow Lite with Zephyr is also supported on Renode. This support enables a test-driven development approach to support new platforms for TensorFlow Lite. Antmicro provides full commercial support for Renode.

Forward-Looking Statements

This article may contain forward-looking statements, including statements relating to expectations for RISC-V core production and development, the ecosystem for these cores, and potential use of these technologies in products. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements, including development challenges or delays, changes in markets, demand, global economic conditions, and other risks and uncertainties listed in Western Digital Corporation’s most recent quarterly and annual reports filed with the Securities and Exchange Commission, to which your attention is directed.

Readers are cautioned not to place undue reliance on these forward-looking statements, and we undertake no obligation to update these forward-looking statements to reflect subsequent events or circumstances.

Ted Marena is chairman of the RISC-V marketing committee at the RISC-V Foundation.

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