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What’s the Difference Between DDR4 and DDR5?

Oct. 1, 2021
Increasing demand for memory is causing DDR4 to fall short of modern application needs, but DDR5 is poised to take performance to the next level.

What you’ll learn:

  • Why we need DDR5.
  • The improvements of DDR5 when compared with DDR4.

The torrent of data created by everything from smartphones to autonomous vehicles converges in the cloud, pushing existing server memory technology to its absolute limit. With millions of servers processing zettabytes of data generated across an increasingly complex landscape of workloads, the need for a new memory standard to meet the voracious bandwidth and capacity demands of increasingly powerful servers grows by the day.

Shifting Gears: DDR4 to DDR5

The current main memory standard—DDR4—was introduced in 2014, and it paved the way for dual inline memory modules (DIMMs) with up to 64 GB in capacity using single-die packages. This was a 4X jump over the 16-GB capacity of DDR3. The overall DDR4 architecture improved memory efficiency and bandwidth from its predecessor.

In today’s modern era, however, DDR4 is falling short of application demands. Data-intensive streaming, video conferencing, online gaming, data analytics, and, of course, AI/ML demand have all risen dramatically. And often the volume is accompanied by an increase in quality (data intensity), such as when video streaming shifts from HD to 4K.

Consequently, hyperscale data centers at the core of the global data network are feeling the crunch. The business world continues to shift workload volume from on premises to the cloud, fueling the doubling in the number of hyperscale data centers since 2015.

DDR5 DRAM helps servers shift to a higher gear by delivering greater bandwidth, increasing capacity, and more. It offers dramatic benefits to server performance through a range of memory performance and architecture improvements (see table).

DDR5 Scales to 6.4 Gb/s

You can never really have enough server bandwidth. DDR5 feeds the need for speed, delivering an immediate 50% increase in bandwidth over DDR4 DIMMs with a data rate of 4.8 Gb/s. Per the JEDEC standard, it will ultimately achieve double the data rate of DDR4 at 6.4 Gb/s. In addition, DDR5 has implemented decision feedback equalization (DFE) to accelerate I/O speeds.

Low Voltage, Low Power

Server performance is limited by the ability to remove heat, so a new memory standard must consider power-reduction techniques at the beginning. Reducing the operating voltage (VDD) from 1.2 V to 1.1 V substantially lowers DDR5’s power consumption. However, a lower operating voltage means a smaller margin for noise immunity, which increases the complexity of design and implementation.

The CA bus moves from stub series terminated logic (SSTL) signaling (which requires an additional voltage rail be provided or a termination derived from VDD that burns static current) to pseudo-open-drain logic (PODL) signaling that uses VDD as termination and draws zero current when the signal is high.

Finally, a new DRAM instruction, Write Pattern (WRP), enables the processor to zero out a 64-byte cache line without any activity on the data lines. The pattern written to the target address is programmable through a Mode Register.

New Power Architecture

With DDR5 DIMMs, power management moves from the motherboard to the DIMM itself. DDR5 DIMMs will have a 12-V power-management IC (PMIC) on the DIMM, allowing for better granularity of system power loading. Server designers now don’t need to provision onboard regulators to support the maximum DIMM loading. Delivery of 12 V to the DIMM reduces IR drop.

The PMIC eases signal integrity and noise challenges, offering better on-DIMM control of the power supply, and helps mitigate the margin loss from a lower operating voltage. The PMIC delivers five distinct voltages to the DIMM ranging from 1.0 to 1.8 V. Two different server PMICs are defined at two distinct peak current levels so that efficiency at expected load can be optimized.

Channel Architecture Update

DDR5 also has a brand new DIMM channel architecture: DDR4 DIMMs have a 72-bit bus, comprised of 64 data bits plus eight ECC bits. With DDR5, each DIMM will have two channels. Each channel will be 40 bits wide: 32 data bits with eight ECC bits. While the data width is the same (64 bits total), having two smaller independent channels improves memory access efficiency.

In the DDR5 DIMM architecture, the left and right sides of the DDR5 DIMM are each served by an independent 40-bit-wide channel that share the registered clock driver (RCD). With DDR4, the RCD provided two output clocks per side, but DDR5’s RCD doubles that, at four output clocks per side. This limits the clock loading to just five DRAM devices, which is half of a single rank (20 bits) on a 2Rx4 DIMM. Providing each half-rank with an independent clock improves signal integrity and helps address the lower noise margin issue raised by lowering the VDD.

Longer Burst Length

By increasing the burst chop and burst length to eight and 16, a single burst can access 64 bytes of data. A single 40-bit-wide channel can thus deliver a typical CPU cache line size, improving concurrency and memory efficiency.

With a longer transfer time of 16-unit intervals, the host can more effectively pipeline read transactions in which the row access time is relatively fixed from generation to generation. Increased parallelism and the ability to pipeline accesses is further enabled by the increase of internal DRAM banks to 32.

Supports Higher-Capacity DRAM

DDR5 supports higher-capacity DRAM devices than its predecessors. With DDR5 buffered DIMMs, the server or system designer can use densities of up to 64-Gb DRAMs in a single-die package. DDR4 maxes out at just 16-Gb DRAM in a single-die package, limiting capacity to 64 GB, whereas DDR5 RDIMMs will be able to achieve 256 GB using single-die package. DIMM capacities greater than this can be achieved by using 3DS DRAMs, where stacks of two to 16 DRAM die (only up to eight for 64 Gb) in one through-silicon-via (TSV) package are supported by the standard.

For the first time, a non-binary density of 24 Gb will be supported between the 16- and 32-Gb densities. This will allow higher capacities, and potentially lower cost per bit, to enter the market faster, and enable server makers to more finely tune their capacity per core. DDR5 also supports features such as on-die ECC, error transparency mode, post-package repair, and read and write CRC modes to bring about these higher-capacity DIMMs.

Bringing It All Together

With these improvements come new design considerations. It’s important to make sure the power delivery network (PDN) can handle the load at higher speeds while maintaining signal integrity. Designers need to ensure motherboards and DIMMs can support the higher signal speeds, too. When performing system-level simulations, signal integrity at all DRAM locations must be checked, and the Command Address Bus requires special attention.

Luckily, DDR5 memory interface chips solve these challenges by improving signal integrity for command and address signals from the memory controller to the DRAMs on DIMM. This reduces the load on the bus, enabling higher-capacity DRAMs on the DIMM with minimal latency impact.

Cloud computing has pushed existing memory technology to its limit. DDR5 was designed to provide for higher capacity and greater bandwidth demanded by data-intensive workloads. With new DRAM device performance, new DIMM architectural features, and a new generation of memory-interface chips, DDR5 memory will power performance in servers coming in 2022 and beyond.

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