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Synopsys Eyes Embedded Processors with VPX2 and VPX3 DSP Cores

Sept. 30, 2021
While the ARC VPX5 processor can run 512-bit vectors to pump more performance out of AI workloads, the VPX2 and VPX3 DSP cores have 128-bits and 256-bits processing engines to save power and area.

Synopsys is expanding its digital signal processor (DSP) family with the ARC 128-bit VPX2 and 256-bit VPX3.

The processors, based on the same VLIW/SIMD architecture as its high-end 512-bit ARC VPX5 core, supply up to two-thirds less power and area. Synopsys said it had designed the VPX2 and VPX3 for chips used in cars, on factory floors, and consumer electronics that can carry out artificial intelligence (AI) and other chores with a high degree of power efficiency. These systems tend only to have as much power as the battery can store.

AI software frequently stores the data it needs to process in the form of a compact unit of data called a vector. The more data that can be stored in a vector, the longer it is. While the VPX5 processor can run 512-bit vectors to wring more performance from AI workloads, the VPX2 and VPX3 cores dial down to 128-bits and 256-bits to save power and area. That opens the door for chip designers to roll out smaller, more power-efficient silicon.

"By expanding the ARC DSP processor portfolio with support for smaller vectors, Synopsys is enabling signal processing and AI in size, power, and thermally-constrained systems," said Jim McGregor, principal analyst at Tirias Research, in a statement.

Synopsys is one of the world's largest vendors of electronic design automation (EDA) tools used to build chips. But it is also a leading player in intellectual property (IP) embedded in systems on a chip (SoCs). Synopsys said its ARC cores are used by over 250 customers globally who supply 2.5 billion ARC-based chips annually. DSPs are generally used to process audio, images, video, or other workloads, but they are also gaining ground in AI.

For Synopsys, power efficiency was a major priority in the VPX2 and VPX3 processor designs. Chip designers can use the DSP cores in single- or dual-core configurations. Under the hood, every core integrates a scalar execution unit and vector units that can run 8-bit, 16-bit, and 32-bit computations. They can also handle half-, single-, and double-precision floating-point formats. Up to three floating-point pipelines are inside each core.

Synopsys plans to start offering the VPX2 and VPX3 DSPs to lead customers in the fourth quarter.

The VPX2 and VPX3 cores bring improvements to the underlying instruction set architecture. It also bolstered the load/store bandwidth to deliver up to double the performance of its previous offerings on DSP workloads.

Synopsys also rolled out the VPX2FS and VPX3FS, which contain a range of functional safety features ideal for chips used in cars or factory floors. For instance, the DSP cores support error-correcting code (ECC) protection for memory and interfaces, as well as internal safety monitors. Furthermore, when placed in pairs, the VPX2FS and VPX3FS can use lockstep mechanisms to add more redundancy and safety to the system, Synopsys said.

The VPX2FS and VPX3FS can be used in automotive-grade chips rated for ASIL-B, ASIL-C, and ASIL-D systems under the ISO 26262 functional safety standard. They are also targeted at medical- and industrial-grade chips.

The safety-focused DSPs will be available to early customers in the first quarter of 2022, the company said.

John Koeter, senior vice president of marketing and strategy for intellectual property (IP) at Synopsys, said the VPX2, VPX3, and VPX5 processor family gives its customers the flexibility to fine-tune designs for a wide range of different end markets. He said Synopsys now supports a complete range of "scalable, software-compatible DSP IP solutions that address the varying performance, power, and area requirements across a chip family."

Synopsys said the VPX2 and VPX3 are supported by its MetaWare development toolset, which ranges from a C/C++ compiler to robust software libraries to accelerate code development and simplify software portability.

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