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Samsung Foundry Delays 3-nm Node to 2022, 2-nm Due by 2025

Oct. 12, 2021
Samsung's 2-nm node will be based on gate-all-around—sometimes called "nanosheet"—transistors, a completely new architecture that is promising performance and power efficiency gains over the FinFET.

Samsung Electronics said its foundry business will start manufacturing chips based on its future 2-nm node by the second half of 2025, according to Siyoung Choi, president and general manager of Samsung Foundry.

The announcement at Samsung’s 2021 Foundry Forum, signals the semiconductor giant plans to remain in the race with TSMC and Intel to develop the world’s most advanced process technologies despite how tough the chip-making business has become in recent years.

Samsung is facing challenge with its latest technology node. The foundry planned to begin rolling out chips based on its 3-nm node in the second half of 2021. But it has been forced to delay the process —its first to use gate-all-around (GAA) transistors—to early 2022.

The 2-nm node will also be based on gate-all-around—what industry insiders sometimes call "nanosheet"—transistors, a completely new architecture that promises major gains in performance and power efficiency.

For the last decade, Samsung and its rivals have rolled out chips with a type of transistor called the FinFET. These transistors are formed by placing fin-shaped flanges of silicon to serve as the channel for current traveling through the tiny electronic switches. A structure called a "gate" controls the delivery of current from the "source" to the "drain" electrode in the transistor. Applying a voltage to the gate switches it on or off. The gate is draped over the silicon fin, surrounding it on three sides and limiting its power leakage.

In the race to roll out smaller, faster, and less power-hungry processors, semiconductor giants such as Intel, Samsung, and TSMC shrink the silicon fins every several years, making it possible to pack more transistors in a chip. But every time they scale the transistors, new challenges come into play that make carrying out computations more difficult.

Because the gate surrounds the rectangular fin on only three sides, a small amount of current can escape from the bottom side when the transistor is turned off. Transistors that refuse to turn off completely waste power and dissipate it as heat that can sap a chip's overall performance.

Foundries are upgrading to gate-all-around technology to reduce the amount of current that can leak out of the transistor and increase the amount of current that it can handle safely. Instead of draping the gate over the channel region of the transistor and covering it on three sides, the fin is flipped on its side so the metal gate can surround the ribbon-shaped channel on all sides, limiting power leakage and allowing it to switch faster.

One of the other advantages of the transistor is that chip manufacturers can adjust the width of the ribbon-shaped channels inside. That lets them fine-tune the transistors for power efficiency, performance, or die area.

Samsung said it would start producing its customers’ first 3-nm chip designs in the first half of 2022, while the second generation of its 3-nm node is due in 2023. The first generation of its unique gate-all-around transistor technology, what it calls the Multi-Bridge-Channel FET or MBCFET, will allow for an up to 35% decrease in area and 30% higher performance or 50% lower power compared to its 5-nm FinFET node.

Last year, Samsung became the first foundry to announce its shift to gate-all-around transistors, and in July, the foundry taped out its first 3-nm test chip, signaling that it is finally close to mass production.

Intel plans to introduce its gate-all-around transistor called the RibbonFET with its 20A process node starting in 2024. In July, the company said it had landed Qualcomm as its first foundry customer for 20A silicon.

It has also started early work on its second-generation RibbonFET technology—called 18A—due out by 2025.

A transition to a new transistor design is a huge undertaking for the semiconductor industry.

Chip foundries need to improve yields—the percentage of undamaged chips that can be carved out of each silicon wafer processed in a fab—to the point where the technology node is profitable. Cadence, Synopsys, and other software vendors need to roll out electronic design automation (EDA) tools to address new rules for floor planning, routing, and placement, as well as the increased variability at advanced nodes. 

Fabless semiconductor firms also need CPU cores and other IPs that can be manufactured with GAA FETs.

Samsung has one of the world’s largest foundry operations globally, including its advanced S1, S3, and S4 fabs in South Korea and its S2 plant in Austin, Texas. Nvidia uses Samsung to manufacture its flagship A100 GPU for the data center market. Samsung has also partnered with Qualcomm to build its 5-nm Snapdragon chips for 5G smartphones. IBM is another key customer.

Dialing in the cost, area, performance, and power of its 3-nm and 2-nm nodes will be key to keeping its customers from fleeing to rivalsand signing new contracts.

While it did not reveal specific details about the improvements over its 3-nm process, chips based on 2-nm will probably have healthy power, performance, and transistor density gains over previous-generation nodes. Samsung said it would use what it learns at the 3-nm node to meet its goals for 2-nm. “Ultimately, we expect the industry’s transition to 2-nm to be smooth thanks to the previous experience with 3-nm,” Choi said.

Executives at Samsung’s foundry business said that its process “maturity” has increased with its 3-nm node, with yields of logic chips closing in on the same level as its 4-nm node, which is in mass production.

If the new node enters mass production in the second half of 2025, smartphones or other devices with 2-nm chips from Samsung will probably not hit the market before the first quarter of 2026.

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