Embedded test technologies got attention on two fronts last week as GOEPEL electronic and JTAG Technologies each debuted new capabilities. GOEPEL said its IP-based ChipVORX technology has been extended to execute bit-error-rate test (BERT) by enabling FPGA-based embedded instruments to perform the BERT function.
JTAG's latest initiative is CoreCommander for FPGAs, which offers a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port (TAP) to proprietary IP cores (for example, DDR and USB controllers) and harness them for test purposes.
GOEPEL's ChipVORX makes use of soft cores to support the test and design validation of high-speed I/O. With the new BERT capability, users can evaluate transmission channel quality and view an eye diagram to facilitate design validation. GOEPEL developed the capability in cooperation with Testonica Lab. Read more here.
JTAG's CoreCommander for FPGAs uses a translator block to access proprietary IP cores through commonly implemented bus structures such as Wishbone, AMBA, Avalon, and CoreConnect. This translator block, provided as a VHDL module, can be either permanently or temporarily programmed into a gate array. Read more here.
GOEPEL's chip-embedded instruments are part of GOEPEL's so called Embedded System Access (ESA) technologies, which support validation, test, and debug as well as programming of complex boards and systems. JTAG's CoreCommander forms part what JTAG calls its range of ETP (Embedded Test and Programming) products, aimed at hardware design and test engineers.
