What you’ll learn:
- Why legacy testing approaches can’t keep pace with today’s silicon requirements
- How the latest software-centric approaches can reduce costs and speed time to market
The industry may be just hitting its stride with 400G optics, but chipset makers already have their sights set on what’s next: 800G. The high-stakes race to bring tomorrow’s ultra-high-density data center, edge, and 5G networking solutions to market has already begun. And stakeholders across the industry are banking on a new generation of application-specific integrated circuits (ASICs) and system-on-a-chip (SOC) technologies to help them win it.
As with all silicon innovations, the path to tomorrow’s chipsets will involve extensive testing and validation. And if you’re among the chipset makers, network vendors, and original design manufacturers building them, you’ve got a big challenge ahead of you. To meet high-pressure market demands, you’ll need to bring new solutions to market more quickly than ever, with fewer cycles, ideally at a lower cost. And you’ll want to avoid the most expensive pitfall in chipset manufacturing: failing to identify issues before designs are baked into silicon instead of after.
If you’re struggling to imagine how you’ll do all this with current testing tools and methodologies, you’re not alone. Many common testing approaches can barely keep up with today’s challenges, much less tomorrow’s. Fortunately, better options have started to emerge. The industry has finally begun shifting to more modern, software-centric approaches based on continuous pre- and post-silicon testing. And this transition couldn’t have come at a better time.
A Driving Need for New Approaches
As the market plans for the Cloud and Edge solutions that will fuel tomorrow’s ultra-dense networks and ultra-high-performance applications, companies are champing at the bit for the latest and greatest silicon. However, designing and validating new chipsets is a notoriously slow, expensive process.
Current silicon development cycles encompass seemingly endless back-and-forth handoffs between design teams and manufacturers, often across continents. The process stretches out over months, sometimes more than a year, at a cost of millions. And that’s assuming you don’t discover a major issue post-release. At which point, you can start the whole process again. Only now, you’ve wasted thousands of hours, disrupted your customers, and (according to the National Institute of Standards and Technologies) increased the cost of fixing the problem by a factor of 30.
Why is this process so fraught? One big reason is that chipset providers continue to rely on dated, inefficient testing approaches. Many still use big, hardware-based Electronic Design Emulation (EDA) systems to emulate silicon. These systems do offer a way to verify IC and printed circuit board designs, but they require developers to perform a huge number of physical tests, including setting up different tests for each port and interface. The process can be so grueling, some chipset makers forego large parts of early-stage verification entirely in favor of post-silicon validation—despite the huge risks and costs of discovering a major bug in a highly adopted product.
A Smarter Path Forward
Clearly, the testing workflows many chip makers have been using are due for an overhaul. The industry needs to standardize on a more modern approach better suited to today’s virtualized, software-centric, cloud-connected technology landscape. One that lets chipmakers discover bugs earlier in the process and correct them before they ever end up in silicon.
The good news is that this shift is already under way. The latest silicon emulation techniques (currently at Layer-1, in the future, beyond) hold the key to cutting costs and inefficiencies in the design process. By reducing reliance on manual physical testing in favor of emulation and automation, chip makers can dramatically simplify and enhance pre-silicon verification and post-silicon validation. And they can shave months off time to market in the process.
Modern EDA systems and emulators leave behind hardware-centric platforms in favor of more flexible virtualized software. Pre-silicon testing workflows have evolved in the same direction, foregoing hardware-based traffic generators with more flexible, easier-to-deploy software solutions. As a result, chip makers can now quickly test thousands of ports. And they can easily, continually reconfigure tests to emulate a wider range of traffic situations and protocols in far less time.
Tests of complex network environments that used to take 50 hours or longer to set up can now be executed in minutes. And, because modern software-based testbeds are more automated and repeatable, the engineers using them no longer need to have extensive specialized expertise in test design. There’s no longer a need to master diverse scripts or write millions of lines of code. Which means chip makers can conduct far more test cases in the same timeframe, while dramatically shrinking regression cycles.
Tomorrow’s most innovative cloud, edge, and Internet of Things applications will require silicon that delivers exceptional performance in the most demanding, high-density scenarios. Which means the pressure to deliver new chip sets faster and more reliably will only continue to grow. Fortunately, testing methodologies are finally moving away from what worked a decade ago and delivering what chip makers and their customers need today.
By embracing more virtualized, automated, and continuous pre- and post-silicon testing, chip makers can:
- Bring new ASIC and SOC solutions to market much more quickly
- Drive down development cycles and costs
- Achieve higher quality standards by identifying and resolving defects during the design phase, instead of after they’re baked into silicon
- Enable more consistent, reusable testing across pre-silicon verification and post-silicon validation
Perhaps most important, by streamlining and modernizing testing, chip makers can perform more exhaustive testing at scale. Which means they can continually develop more specialized and complex chipsets—faster, more efficiently, and with higher quality. As they do, the industry will gain ever more powerful tools to bring world-changing technology innovations to customers.